JP6885787B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP6885787B2 JP6885787B2 JP2017104342A JP2017104342A JP6885787B2 JP 6885787 B2 JP6885787 B2 JP 6885787B2 JP 2017104342 A JP2017104342 A JP 2017104342A JP 2017104342 A JP2017104342 A JP 2017104342A JP 6885787 B2 JP6885787 B2 JP 6885787B2
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- 239000004065 semiconductor Substances 0.000 title claims description 182
- 238000000034 method Methods 0.000 title claims description 86
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000926 separation method Methods 0.000 claims description 85
- 239000000758 substrate Substances 0.000 claims description 37
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 25
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 238000005229 chemical vapour deposition Methods 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 238000003860 storage Methods 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims 4
- 239000003989 dielectric material Substances 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 30
- 229920005591 polysilicon Polymers 0.000 description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 28
- 239000010410 layer Substances 0.000 description 28
- 229910052814 silicon oxide Inorganic materials 0.000 description 28
- 238000005530 etching Methods 0.000 description 27
- 125000006850 spacer group Chemical group 0.000 description 16
- 238000002347 injection Methods 0.000 description 12
- 239000007924 injection Substances 0.000 description 12
- 239000012535 impurity Substances 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 11
- 238000001312 dry etching Methods 0.000 description 10
- 229910021332 silicide Inorganic materials 0.000 description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 10
- 239000013256 coordination polymer Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000001039 wet etching Methods 0.000 description 5
- 239000002784 hot electron Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910010038 TiAl Inorganic materials 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000012447 hatching Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 1
- 238000004335 scaling law Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Description
[構造説明]
以下、図面を参照しながら本実施の形態の半導体装置(不揮発性メモリ装置、半導体記憶装置)の構造について説明する。本実施の形態の半導体装置は、スプリットゲート型のメモリセルを有する。即ち、本実施の形態のメモリセルは、制御ゲート電極CGを有する制御トランジスタと、制御トランジスタに接続され、メモリゲート電極MGを有するメモリトランジスタと、を有する。なお、ここで言うトランジスタは、MISFETとも呼ばれる。
図1は、本実施の形態の半導体装置のメモリセルの構成を示す斜視図である。図2は、本実施の形態の半導体装置のメモリセルを示す断面図であり、図3は、平面図である。図2の左の図は、図3のA−A断面、中央の図は、図3のB−B断面、右の図は、図3のC−C断面に対応する。なお、B−B断面部は、メモリゲート電極MGの形成領域であり、C−C断面部は、制御ゲート電極CGの形成領域である。
次いで、メモリセルの基本的な動作の一例について説明する。メモリセルの動作として、(1)読出し、(2)消去、(3)書込みの3つの動作について説明する。但し、これらの動作の定義には種々のものがあり、特に消去動作と書込み動作については、逆の動作として定義されることもある。
以下に、図6〜図31を用いて、本実施の形態の半導体装置の製造方法について説明する。図6〜図31は、本実施の形態の半導体装置の形成工程中の断面図または斜視図である。
まず、図6〜図17を参照しながらフィンFの形成工程を説明する。まず、図6に示すように、半導体基板SBを用意し、半導体基板SBの主面上に、絶縁膜IF1、絶縁膜IF2および半導体膜SI1を順に形成する。半導体基板SBは、例えば1〜10Ωcm程度の比抵抗を有するp型の単結晶シリコンなどからなる。絶縁膜IF1は、例えば酸化シリコン膜からなり、例えば、熱酸化法またはCVD(Chemical Vapor Deposition)法を用いて形成することができる。絶縁膜IF1の膜厚は、2〜10nm程度である。絶縁膜IF2は、例えば窒化シリコン膜からなり、その膜厚は、20〜100nm程度である。絶縁膜IF2は、例えばCVD法により形成することができる。半導体膜SI1は、例えばシリコン膜からなり、例えばCVD法により形成する。半導体膜SI1の膜厚は、例えば20〜200nmである。
次いで、図18〜図31を参照しながら素子分離部STの形成工程以降の工程を説明する。図18は、図17の状態からハードマスクHM1をエッチングなどにより除去し、フィンF上に絶縁膜IF1およびIF2が残存している状態を示す。なお、図18に示すように、フィンFの側面がテーパー状となっていてもよい。図18の状態から、図19に示すように、半導体基板SBの上に、フィン間の溝(分離溝)G、フィンF、絶縁膜IF1およびIF2を完全に埋めるように、酸化シリコン膜などからなる絶縁膜を堆積する。続いて、この絶縁膜に対してCMP(Chemical Mechanical Polishing)法による研磨処理を行い、絶縁膜IF2の上面を露出させる。なお、図17の状態からハードマスクHM1を除去しなかった場合においても、研磨処理によりハードマスクHM1は消失する。
実施の形態1の半導体装置においては、制御ゲート電極CGをポリシリコン膜PS2で構成したが、制御ゲート電極CGをメタル電極膜で構成してもよい。このように、ゲート電極をメタル電極膜で構成し、さらに、ゲート絶縁膜をhigh−k絶縁膜で構成したトランジスタを、high−k/メタル構成を適用したトランジスタと言う。high−k絶縁膜とは、例えば窒化シリコン膜よりも比誘電率が高い高誘電率膜(高誘電体膜)である。
本実施の形態の半導体装置(図37)においても、メモリセルは、制御ゲート電極CGを有する制御トランジスタと、メモリゲート電極MGを有するメモリトランジスタとからなる。また、メモリゲート電極MGおよび制御ゲート電極CGの合成パターンの側壁部には、絶縁膜からなるサイドウォールSW2が形成されている。
以下に、図32〜図37を用いて、本実施の形態の半導体装置の製造方法について説明する。
実施の形態1においては、メモリゲート電極MGの下層の絶縁膜ONO(11、12、13)中にサイドエッチングを考慮しつつ、制御ゲート電極CGの形成領域の素子分離部STの上面と、メモリゲート電極MGの形成領域の素子分離部STの上面との高低差を10nm以下とした。これに対し、本実施の形態では、絶縁膜ONOの側面に、サイドウォールSW10を設け、素子分離部STの上面の後退量(上記高低差)を大きく確保する。
実施の形態1〜3においては、制御ゲート電極CGの下方の素子分離部STの上面と、メモリゲート電極MGの下方の素子分離部STの上面とを、均一で平坦な面として説明したが、各領域の上面に凸凹があってもよい。
12 中層絶縁膜(絶縁膜)
13 上層絶縁膜(絶縁膜)
15 絶縁膜
CG 制御ゲート電極
CGI 制御ゲート絶縁膜(ゲート絶縁膜)
CP キャップ絶縁膜
D1、D2、D3 高低差(後退量)
EX n−型半導体領域
F フィン
FH1、FH2、FH3 フィン高さ
G 溝
HM1 ハードマスク
IF1 絶縁膜
IF2 絶縁膜
IF3 絶縁膜
IL1 層間絶縁膜
L ライン
M1 配線
MD ドレイン領域
MG メモリゲート電極
MS ソース領域
ONO メモリゲート絶縁膜(ゲート絶縁膜、絶縁膜)
P1 プラグ
PR2 フォトレジスト膜
PS1 ポリシリコン膜
PS2 ポリシリコン膜
PW p型ウエル
SB 半導体基板
SD n+型半導体領域
SI1 半導体膜
SIL 金属シリサイド膜
SP スペーサ
ST 素子分離部
SW1 サイドウォール
SW2 サイドウォール
SW10 サイドウォール
Claims (10)
- 第1方向に延在する直方体状の第1フィンと、
前記第1フィンと離間して配置され、前記第1方向に延在する直方体状の第2フィンと、
前記第1フィンと前記第2フィンとの間に配置され、かつ、その高さが前記第1フィンおよび前記第2フィンの高さより低い、素子分離部と、
前記第1フィン、前記素子分離部および前記第2フィンの上に、電荷蓄積部を有する第1ゲート絶縁膜を介して配置され、前記第1方向と交差する第2方向に延在する第1ゲート電極と、
前記第1フィン、前記素子分離部および前記第2フィンの上に第2ゲート絶縁膜を介して配置され、前記第1方向と交差する前記第2方向に延在し、前記第1ゲート電極と並んで配置された第2ゲート電極と、
を有し、
前記第1ゲート電極の下方の前記素子分離部の高さは、前記第2ゲート電極の下方の前記素子分離部の高さより高く、
前記第1ゲート絶縁膜は、前記第1フィン上に形成された第1膜と、前記第1膜上に形成され、前記電荷蓄積部となる第2膜と、前記第2膜上に形成された第3膜とを有し、
前記第1ゲート電極の下方の前記素子分離部の高さと、前記第2ゲート電極の下方の前記素子分離部の高さの差は、5nm以上10nm以下である、半導体装置。 - 請求項1記載の半導体装置において、
前記第1ゲート電極および前記第2ゲート電極は、シリコンよりなる、半導体装置。 - 請求項2記載の半導体装置において、
前記第1膜は、熱酸化膜であり、前記素子分離部は、CVD膜よりなる、半導体装置。 - 請求項3記載の半導体装置において、
前記第2ゲート電極は、金属膜よりなり、前記第2ゲート絶縁膜は、窒化シリコンより誘電率の高い高誘電体よりなる、半導体装置。 - 請求項1記載の半導体装置において、
前記第1ゲート電極の下方の前記素子分離部の高さは、前記第1膜と前記素子分離部との第1合成部であって、前記第1合成部の膜厚が増加し始める部位の高さに対応し、
前記第2ゲート電極の下方の前記素子分離部の高さは、前記第2ゲート絶縁膜と前記素子分離部との第2合成部であって、前記第2合成部の膜厚が増加し始める部位の高さに対応する、半導体装置。 - (a)第1方向に延在する第1フィン形成領域と、前記第1フィン形成領域と離間して配置され、前記第1方向に延在する第2フィン形成領域と、を有する半導体基板の、前記第1フィン形成領域と前記第2フィン形成領域との間に分離溝を形成するとともに、第1フィンと第2フィンを形成する工程、
(b)前記分離溝の内部に分離絶縁膜を埋め込むことにより素子分離部を形成する工程、
(c)前記素子分離部の表面を後退させる工程、
(d)前記半導体基板上に電荷蓄積部を有する第1絶縁膜を形成し、さらに、前記第1絶縁膜上に、第1導電性膜を形成し加工することにより、前記第1フィン、前記素子分離部および前記第2フィンの上方に、前記第1方向と交差する第2方向に延在する第1ゲート電極を形成する工程、
(e)前記半導体基板上に第2絶縁膜を形成し、さらに、前記第2絶縁膜上に、第2導電性膜を形成し加工することにより、前記第1フィン、前記素子分離部および前記第2フィンの上方に、前記第1方向と交差する前記第2方向に延在する第2ゲート電極を形成する工程、
を有し、
前記(e)工程は、前記(d)工程より後に行われ、
前記(d)工程の後において、前記第1ゲート電極の下方の前記素子分離部の高さは、前記第2ゲート電極の下方の前記素子分離部の高さより高く、
前記(d)工程は、前記第1絶縁膜として、前記第1フィン上に第1膜を形成し、前記第1膜上に、前記電荷蓄積部となる第2膜を形成し、前記第2膜上に第3膜を形成する工程を有し、
前記(d)工程の後において、前記第1ゲート電極の下方の前記素子分離部の高さと、前記第2ゲート電極の下方の前記素子分離部の高さの差は、5nm以上10nm以下である、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記(d)工程は、
(d1)前記第1ゲート電極の形成領域および前記第2ゲート電極の形成領域上に、前記第1絶縁膜および前記第1導電性膜を形成する工程、
(d2)前記第1ゲート電極の形成領域に、前記第1絶縁膜および前記第1導電性膜を残存させ、前記第2ゲート電極の形成領域の、前記第1絶縁膜および前記第1導電性膜を除去する工程、
を有し、
前記(d2)工程において、前記第2ゲート電極の形成領域において露出した前記素子分離部の表面が後退する、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記第1ゲート電極および前記第2ゲート電極は、シリコンよりなる、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記(d)工程の前記第1膜は、熱酸化により形成され、
前記(b)工程の前記分離絶縁膜は、CVD法により形成される、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記第1ゲート電極の下方の前記素子分離部の高さは、前記第1膜と前記素子分離部との第1合成部であって、前記第1合成部の膜厚が増加し始める部位の高さに対応し、
前記第2ゲート電極の下方の前記素子分離部の高さは、前記第2絶縁膜と前記素子分離部との第2合成部であって、前記第2合成部の膜厚が増加し始める部位の高さに対応する、半導体装置の製造方法。
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- 2018-03-20 EP EP18162904.9A patent/EP3407377A1/en not_active Withdrawn
- 2018-05-15 TW TW107116386A patent/TWI772421B/zh active
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Publication number | Publication date |
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US10580785B2 (en) | 2020-03-03 |
CN108933144A (zh) | 2018-12-04 |
KR20180129659A (ko) | 2018-12-05 |
JP2018200936A (ja) | 2018-12-20 |
TWI772421B (zh) | 2022-08-01 |
CN108933144B (zh) | 2023-12-05 |
TW201901927A (zh) | 2019-01-01 |
US20180342526A1 (en) | 2018-11-29 |
EP3407377A1 (en) | 2018-11-28 |
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