JP6652451B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6652451B2 JP6652451B2 JP2016117617A JP2016117617A JP6652451B2 JP 6652451 B2 JP6652451 B2 JP 6652451B2 JP 2016117617 A JP2016117617 A JP 2016117617A JP 2016117617 A JP2016117617 A JP 2016117617A JP 6652451 B2 JP6652451 B2 JP 6652451B2
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Description
<半導体チップのレイアウト構成例>
本実施の形態における不揮発性メモリを有する半導体装置について図面を参照しながら説明する。まず、不揮発性メモリを含むシステムが形成された半導体装置(半導体チップ)のレイアウト構成について説明する。図1は、本実施の形態における半導体チップCHPのレイアウト構成例を示す概略図である。図1において、半導体チップCHPは、CPU(Central Processing Unit)CC1、RAM(Random Access Memory)CC2、アナログ回路CC3を有している。また、半導体チップCHPは、EEPROM(Electrically Erasable Programmable Read Only Memory)CC4、フラッシュメモリCC5およびI/O(Input/Output)回路CC6を有し、半導体装置を構成している。
以下に、図2〜図5を用いて、本実施の形態の半導体装置の構造について説明する。図2は、本実施の形態における半導体装置の平面図である。図3は、本実施の形態における半導体装置の斜視図である。図4および図5は、本実施の形態における半導体装置の断面図である。なお、図3、図5では、ウェルの図示を省略する。また、図5では、ソース・ドレイン領域の図示を省略する。
nMIS領域1BおよびpMIS領域1Cに形成されたエピタキシャル層EP1、EP2のそれぞれの上面であって、シリサイド層S3を介してプラグPG2に接続された面の位置は、シリサイド層S1の上面であって、プラグPG1に接続された面の位置よりも高い。これは、フィンFA上に形成されたシリサイド層S1の膜厚よりも、フィンFB上またはフィンFC上に形成されたエピタキシャル層EP1、EP2のそれぞれの膜厚の方が大きいためである。
以下に、図6〜図53を用いて、本実施の形態の半導体装置の製造方法について説明する。図6、図8、図10、図12、図15、図17、図19、図20〜図40および図42〜図53は、本実施の形態の半導体装置の形成工程中の断面図である。図7、図9、図11、図13、図14、図16および図18は、本実施の形態の半導体装置の形成工程中の斜視図である。図41は、本実施の形態の半導体装置の形成工程に用いるスパッタリング装置の模式的な平面図である。図8、図10、図12、図15、図17および図19は、図7、図9、図11、図14、図16および図18の同じ位置におけるY方向に沿う断面を示す図である。上記斜視図、図42および図44では、ウェルの図示を省略する。
次に、不揮発性メモリの動作例について、図54および図55を参照して説明する。
次に、本実施の形態の半導体装置の製造方法の主要な特徴および効果について、比較例として図58を用いて説明する。図58は、比較例の半導体装置の製造工程中の断面図であって、図42に示す断面図に対応する。
以下に、図56および図57を用いて、本実施の形態2の半導体装置の製造方法について説明する。図56および図57は、本実施の形態2の半導体装置の形成工程中の断面図である。なお、図57では図を分かりやすくするため、図56に示す積層膜である絶縁膜ONを1つの膜として示している。
1B nMIS領域
1C pMIS領域
CG 制御ゲート電極
D1〜D3 拡散領域
EI 素子分離膜
EX1〜EX3 エクステンション領域
FA〜FC フィン
G1、G2 ゲート電極
GF ゲート絶縁膜
MC メモリセル
MG メモリゲート電極
ON 絶縁膜(ONO膜)
QN n型トランジスタ
QP p型トランジスタ
S1〜S3、SS シリサイド層
SB 半導体基板
Claims (15)
- 主面に沿って並ぶ第1領域および第2領域を有する半導体基板と、
前記第1領域の前記半導体基板の一部分であって、前記半導体基板の上面から突出し、前記半導体基板の前記主面に沿う第1方向に延在する第1突出部と、
前記第1突出部の上面上に第1絶縁膜を介して形成され、前記第1方向に直交する第2方向に延在する第1ゲート電極と、
前記第1突出部の前記上面上に電荷蓄積部である第2絶縁膜を介して形成され、前記第1ゲート電極の一方の側壁に前記第2絶縁膜を介して隣接し、前記第2方向に延在する第2ゲート電極と、
前記第1ゲート電極および前記第2ゲート電極からなるパターンを前記第1方向において挟むように前記第1突出部の前記上面に形成された第1ソース・ドレイン領域と、
前記第2領域の前記半導体基板の一部分であって、前記半導体基板の前記上面から突出し、前記第1方向に延在する第2突出部と、
前記第2突出部の上面上に第3絶縁膜を介して形成され、前記第2方向に延在する第3ゲート電極と、
前記第3ゲート電極を前記第1方向において挟むように前記第2突出部の前記上面に形成された第2ソース・ドレイン領域と、
前記第1ソース・ドレイン領域のそれぞれの上面および側壁を覆い、前記第1突出部に接する第1シリサイド層と、
前記第2ソース・ドレイン領域のそれぞれの上面および側壁を覆い、前記第2突出部に接する半導体層と、
を有し、
前記第1ゲート電極、前記第2ゲート電極および前記第1ソース・ドレイン領域は、不揮発性記憶素子を構成し、
前記第3ゲート電極および前記第2ソース・ドレイン領域は、トランジスタを構成する、半導体装置。 - 請求項1記載の半導体装置において、
前記半導体層の上面の位置は、前記第1シリサイド層の上面の位置よりも高い、半導体装置。 - 請求項1記載の半導体装置において、
前記半導体基板上に形成され、前記不揮発性記憶素子および前記トランジスタを覆う第4絶縁膜と、
前記第4絶縁膜を貫通し、前記第1シリサイド層を介して、前記第1ソース・ドレイン領域に電気的に接続された第1接続部と、
前記第4絶縁膜を貫通し、前記第2ソース・ドレイン領域に電気的に接続された第2接続部と、
をさらに有し、
前記第2接続部の底面の位置は、前記第1接続部の底面の位置よりも高い、半導体装置。 - 請求項3記載の半導体装置において、
前記第1接続部と前記第1シリサイド層とは、互いに接しており、
前記第2接続部は、前記第2接続部および前記半導体層の間に形成された第2シリサイド層と前記半導体層とを介して前記第2突出部内の前記第2ソース・ドレイン領域に接続されている、半導体装置。 - 請求項4記載の半導体装置において、
前記第2接続部の横の前記半導体層の前記上面は、前記第2シリサイド層から露出している、半導体装置。 - 請求項4記載の半導体装置において、
前記第1シリサイド層は、ニッケルシリサイドからなり、前記第2シリサイド層は、チタンシリサイドからなる、半導体装置。 - 請求項3記載の半導体装置において、
前記第1接続部と前記第1シリサイド層との間には、チタンを含む第1金属膜が介在しており、
前記第2接続部は、前記第2接続部および前記半導体層の間に形成された第2シリサイド層と前記半導体層とを介して前記第2突出部内の前記第2ソース・ドレイン領域に接続されている、半導体装置。 - 請求項1記載の半導体装置において、
前記半導体層は、前記第2ソース・ドレイン領域の一部を構成している、半導体装置。 - 請求項1記載の半導体装置において、
前記第3ゲート電極は、第2金属膜を含む、半導体装置。 - 請求項1記載の半導体装置において、
前記第1ゲート電極は、第3金属膜を含み、前記第2ゲート電極は、第4金属膜を含む、半導体装置。 - (a)半導体基板を準備する工程、
(b)前記半導体基板の上面の一部を後退させることで、前記半導体基板の一部分であって、前記半導体基板の前記上面から突出し、前記半導体基板の前記上面に沿う第1方向に延在する第1突出部と、前記半導体基板の前記上面から突出し、前記第1方向に延在する第2突出部とを形成する工程、
(c)前記第1突出部および前記第2突出部の間の溝内を埋め込む素子分離膜を形成する工程、
(d)前記(c)工程の後、前記第1突出部の直上に第1絶縁膜を介して第1ゲート電極を形成し、前記第1ゲート電極の一方の側壁に電荷蓄積部である第2絶縁膜を介して隣接する領域の前記第1突出部の直上に前記第2絶縁膜を介して第2ゲート電極を形成し、前記第2突出部の直上に第3絶縁膜を介して第3ゲート電極を形成する工程、
(e)前記第3ゲート電極の横の前記第2突出部の上面および側壁を覆うエピタキシャル層を形成する工程、
(f)前記第3ゲート電極の横の前記第2突出部の上面に第2ソース・ドレイン領域を形成する工程、
(g)前記第1ゲート電極および前記第2ゲート電極からなるパターンの横の前記第1突出部の上面に第1ソース・ドレイン領域を形成する工程、
(h)前記(g)工程の後、前記第2突出部を保護膜により覆った状態で、前記パターンの横の前記第1ソース・ドレイン領域のそれぞれの上面および側壁を覆う第1シリサイド層を形成する工程、
を有し、
前記第1ゲート電極、前記第2ゲート電極および前記第1ソース・ドレイン領域は、不揮発性記憶素子を構成し、
前記第3ゲート電極および前記第2ソース・ドレイン領域は、トランジスタを構成する、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記エピタキシャル層の上面の位置は、前記第1シリサイド層の上面の位置よりも高い、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記(h)工程は、
(h1)前記第2突出部を保護膜により覆う工程、
(h2)前記(h1)工程の後、第1熱処理を行って前記第1突出部を加熱した状態で、前記第1突出部を覆う金属膜を形成することで、前記金属膜と前記第1突出部の表面とを反応させ、これにより前記金属膜と前記第1突出部の表面との間に第3シリサイド層を形成する工程、
(h3)前記(h2)工程の後、第2熱処理を行うことで、前記金属膜と前記第1突出部の表面とを反応させ、これにより前記第1シリサイド層を形成する工程、
を有する、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(h2)工程では、前記第1突出部の側壁を覆う前記金属膜は、前記側壁に沿う方向において互いに離間して並ぶ複数の膜からなる、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(h2)工程は、
(h4)熱処理用チャンバ内で前記第1熱処理を行う工程、
(h5)前記(h4)工程の後、前記半導体基板を、前記熱処理用チャンバ内から成膜用チャンバ内まで真空状態が維持された経路を通って搬送する工程、
(h6)前記(h5)工程の後、前記成膜用チャンバ内でスパッタリング法により前記金属膜の形成を行う工程、
を有する、半導体装置の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
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JP2016117617A JP6652451B2 (ja) | 2016-06-14 | 2016-06-14 | 半導体装置およびその製造方法 |
US15/482,239 US9899403B2 (en) | 2016-06-14 | 2017-04-07 | Semiconductor device and method of manufacturing the same |
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TW106118450A TW201810677A (zh) | 2016-06-14 | 2017-06-05 | 半導體裝置及其製造方法 |
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JP7053388B2 (ja) * | 2018-06-28 | 2022-04-12 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
CN110828460B (zh) * | 2018-08-14 | 2022-07-19 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件及其形成方法 |
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US9899403B2 (en) | 2018-02-20 |
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CN107507864A (zh) | 2017-12-22 |
US20180166459A1 (en) | 2018-06-14 |
JP2017224666A (ja) | 2017-12-21 |
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