JP2019121633A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2019121633A JP2019121633A JP2017253646A JP2017253646A JP2019121633A JP 2019121633 A JP2019121633 A JP 2019121633A JP 2017253646 A JP2017253646 A JP 2017253646A JP 2017253646 A JP2017253646 A JP 2017253646A JP 2019121633 A JP2019121633 A JP 2019121633A
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Abstract
Description
<半導体チップのレイアウト構成例>
本実施の形態における不揮発性メモリである強誘電体メモリを有する半導体装置について図1〜図4を参照しながら説明する。図1は、本実施の形態の半導体装置が搭載された半導体チップのレイアウト構成例を示す概略図である。図2は、本実施の形態である半導体装置を示す断面図である。図3は、本実施の形態である半導体装置の一部を示す拡大断面図である。図4は、本実施の形態である半導体装置において、「書込」、「消去」および「読出」時における選択メモリセルの各部位への電圧の印加条件の一例を示す表である。
図2には、本実施の形態のメモリセルMC1とn型トランジスタQ1とを示している。図2の左側には、不揮発性メモリである強誘電体メモリを構成するメモリセルMC1が形成されたメモリセル領域MRを示している。また、図2の右側には、n型のMISFET(Metal Insulator Semiconductor Field Effect Transistor、MIS型電界効果トランジスタ)であるn型トランジスタQ1が形成されたロジック回路領域(周辺回路領域)LRを示している。周辺回路とは、不揮発性メモリ以外の回路である。周辺回路は、例えば、メモリモジュール内では、制御回路、センスアンプ、カラムデコーダ、ロウデコーダ、モジュール外との入出力回路または電源回路などであり、メモリモジュール外ではCPUなどのプロセッサ、各種アナログ回路、SRAM(Static Random Access Memory)メモリモジュール、または外部入出力回路などである。ロジック回路領域LRに形成されているn型トランジスタは、メモリセルMC1よりも低い電圧で駆動する低耐圧MISFETである。
次に、不揮発性メモリの動作例について、図4を参照して説明する。
次に、本実施の形態の半導体装置の効果について、図75を用いて説明する。図75は、比較例の半導体装置である強誘電体メモリのメモリセルMCAを示す断面図である。
以下に、図5〜図20を用いて、本実施の形態の半導体装置の製造方法について説明する。図5〜図20は、本実施の形態の半導体装置の形成工程中の断面図である。図5〜図20では、左側から右側に向かって順に並ぶメモリセル領域MRおよびロジック回路領域LRを示している。
次に、本実施の形態の半導体装置の製造方法の効果について説明する。
本変形例では、界面層である常誘電体層と半導体基板の主面との間に薄い絶縁膜を形成することについて説明する。
本変形例では、界面層と強誘電体膜との間に金属膜をさらに挿入する場合について説明する。
<半導体装置の構造>
以下に、図25〜図28を用いて、本実施の形態2の半導体装置の構造について説明する。図25は、本実施の形態における半導体装置の平面図である。図26は、本実施の形態における半導体装置の斜視図である。図27および図28は、本実施の形態における半導体装置の断面図である。なお、図26、図28では、ウェルの図示を省略する。また、図28では、ソース・ドレイン領域の図示を省略する。
次に、不揮発性メモリの動作例について、図29を参照して説明する。
本実施の形態の半導体装置では、前記実施の形態1の半導体装置と同様の効果を得ることができる。
以下に、図30〜図74を用いて、本実施の形態の半導体装置の製造方法について説明する。図30、図32、図34、図36、図39、図41および図43〜図74は、本実施の形態の半導体装置の形成工程中の断面図である。図31、図33、図35、図37、図38、図40および図42は、本実施の形態の半導体装置の形成工程中の斜視図である。図32、図34、図36、図39、図41および図43は、図31、図33、図35、図38、図40および図42の同じ位置におけるY方向に沿う断面を示す図である。上記斜視図では、ウェルの図示を省略する。
次に、本実施の形態の半導体装置の製造方法の効果について説明する。
D1〜D3 拡散領域
EI 素子分離領域
EX1〜EX3 エクステンション領域
G1、G2、GE ゲート電極
GF、GI ゲート絶縁膜
HK1 常誘電体膜
HK2 強誘電体膜
LR ロジック回路領域
MC1、MC2、MCA メモリセル
MF1〜MF6 金属膜
MR メモリセル領域
Q1 n型トランジスタ
SB 半導体基板
Claims (15)
- 半導体基板と、
前記半導体基板上に形成された第1絶縁膜と、
前記第1絶縁膜上に形成された強誘電体膜と、
前記強誘電体膜上に形成された第1ゲート電極と、
前記第1ゲート電極を挟むように前記半導体基板の上面に形成されたソース・ドレイン領域と、
を有し、
前記強誘電体膜は、第1酸化ハフニウム膜から成り、
前記第1絶縁膜は、窒化シリコンより高い誘電率を有している、半導体装置。 - 請求項1記載の半導体装置において、
前記第1絶縁膜は、第2酸化ハフニウム膜から成る常誘電体膜である、半導体装置。 - 請求項1記載の半導体装置において、
前記強誘電体膜の膜厚は、前記第1絶縁膜の膜厚よりも大きい、半導体装置。 - 請求項1記載の半導体装置において、
前記強誘電体膜を構成する複数の第1結晶の平均粒径は、前記第1絶縁膜を構成する複数の第2結晶の平均粒径よりも大きい、半導体装置。 - 請求項1記載の半導体装置において、
前記強誘電体膜の上面の凹凸は、前記第1絶縁膜の上面の凹凸よりも大きい、半導体装置。 - 請求項1記載の半導体装置において、
前記強誘電体膜および前記第1絶縁膜は、同じ材料から成る、半導体装置。 - 請求項6記載の半導体装置において、
前記強誘電体膜は、主に、結晶相が直方晶である第1結晶から成り、前記第1絶縁膜は、主に、結晶相が直方晶ではない第2結晶から成る、半導体装置。 - 請求項1記載の半導体装置において、
前記第1絶縁膜の不純物濃度は、前記強誘電体膜の不純物濃度よりも低い、半導体装置。 - 請求項1記載の半導体装置において、
前記強誘電体膜と前記第1ゲート電極との間に、金属膜がさらに形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1ゲート電極の一方の側面に前記第1絶縁膜および前記強誘電体膜を介して隣り合い、前記半導体基板の前記上面上に第2絶縁膜を介して設けられた第2ゲート電極をさらに有し、
前記第1ゲート電極、前記第2ゲート電極および前記ソース・ドレイン領域は、不揮発性記憶素子を構成している、半導体装置。 - 請求項10記載の半導体装置において、
前記半導体基板の一部分であって、前記半導体基板の前記上面から突出し、前記半導体基板の前記上面に沿う第1方向に延在する突出部をさらに有し、
前記第1ゲート電極および前記第2ゲート電極のそれぞれは、前記第1方向に直交する第2方向に延在しており、前記ソース・ドレイン領域は、前記第1ゲート電極および前記第2ゲート電極から成るパターンを前記第1方向において挟むように前記突出部の表面に形成されている、半導体装置。 - (a)半導体基板を準備する工程、
(b)前記半導体基板上に非結晶状態の第1絶縁膜を形成する工程、
(c)第1熱処理を行うことで、前記第1絶縁膜を結晶化する工程、
(d)前記(c)工程の後、前記第1絶縁膜上に非結晶状態の第2絶縁膜を形成する工程、
(e)前記第2絶縁膜にマイクロ波を照射して第2熱処理を行い、前記第2絶縁膜を結晶化することで強誘電体膜を形成する工程、
(f)前記強誘電体膜上に、第1ゲート電極を形成する工程、
(g)前記第1ゲート電極の横の前記半導体基板の上面にソース・ドレイン領域を形成する工程、
を有し、
前記強誘電体膜は、酸化ハフニウム膜から成り、
前記第1絶縁膜は、窒化シリコンより高い誘電率を有している、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記(e)工程では、前記マイクロ波の電場が前記半導体基板の前記上面に対して垂直な方向に振動するように、前記マイクロ波を前記第2絶縁膜に照射する、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
前記(e)工程では、300〜400℃の温度範囲で前記第2熱処理を行う、半導体装置の製造方法。 - 請求項12記載の半導体装置の製造方法において、
(a1)前記(a)工程の後、前記(b)工程の前に、前記半導体基板の前記上面の一部を後退させることで、前記半導体基板の一部分であって、前記半導体基板の前記上面から突出し、前記半導体基板の前記上面に沿う第1方向に延在する突出部を形成する工程、
(a2)前記突出部上を跨いで、前記第1方向に直交する第2方向に延在する第2ゲート電極を、前記突出部上に第3絶縁膜を介して形成する工程、
をさらに有し、
前記(b)工程では、前記突出部の直上に前記第1絶縁膜を形成し、
前記(d)工程では、前記突出部の直上に前記第2絶縁膜を形成し、
前記(f)工程では、前記第2ゲート電極に対し前記第1方向で前記第1絶縁膜および前記強誘電体膜を介して隣り合う前記第1ゲート電極を形成し、
前記(g)工程では、前記ソース・ドレイン領域を、前記第1ゲート電極および前記第2ゲート電極から成るパターンを前記第1方向において挟むように前記突出部の表面に形成し、
前記第1ゲート電極、前記第2ゲート電極および前記ソース・ドレイン領域は、不揮発性記憶素子を構成している、半導体装置の製造方法。
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CN107240606A (zh) * | 2017-06-08 | 2017-10-10 | 湘潭大学 | 一种铁电场效应晶体管及其制备方法 |
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US11335702B1 (en) | 2020-11-13 | 2022-05-17 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
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US10818769B2 (en) | 2020-10-27 |
US20190207009A1 (en) | 2019-07-04 |
CN109979997A (zh) | 2019-07-05 |
TW201941437A (zh) | 2019-10-16 |
JP6920192B2 (ja) | 2021-08-18 |
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