JP6750994B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP6750994B2 JP6750994B2 JP2016191808A JP2016191808A JP6750994B2 JP 6750994 B2 JP6750994 B2 JP 6750994B2 JP 2016191808 A JP2016191808 A JP 2016191808A JP 2016191808 A JP2016191808 A JP 2016191808A JP 6750994 B2 JP6750994 B2 JP 6750994B2
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Description
<半導体チップのレイアウト構成例>
本実施の形態における不揮発性メモリを有する半導体装置について図面を参照しながら説明する。まず、不揮発性メモリを含むシステムが形成された半導体装置(半導体チップ)のレイアウト構成について説明する。図1は、本実施の形態における半導体チップCHPのレイアウト構成例を示す概略図である。図1において、半導体チップCHPは、CPU(Central Processing Unit)CC1、RAM(Random Access Memory)CC2、アナログ回路CC3を有している。また、半導体チップCHPは、EEPROM(Electrically Erasable Programmable Read Only Memory)CC4、フラッシュメモリCC5およびI/O(Input/Output)回路CC6を有し、半導体装置を構成している。
以下に、図2〜図6を用いて、本実施の形態の半導体装置の構造について説明する。図2は、本実施の形態における半導体装置の平面図である。図3は、本実施の形態における半導体装置の斜視図である。図4および図6は、本実施の形態における半導体装置の断面図である。図5は、本実施の形態における半導体装置の平面図である。図4では、図2のA−A線およびB−B線のそれぞれにおける断面を示しており、図6では、図5のC−C線における断面を示している。図3では、半導体基板上の層間絶縁膜、シリサイド層および配線、並びに、半導体基板内のソース・ドレイン領域およびウェルの図示を省略する。
次に、不揮発性メモリの動作例について、図25および図26を参照して説明する。
以下に、図7〜図24を用いて、本実施の形態の半導体装置の製造方法について説明する。図7〜図24は、本実施の形態の半導体装置の形成工程中の断面図である。図7〜図11は、Y方向(図2参照)に沿う断面を示す図である。図12〜図24では、図4と同様に、図の左側にX方向(図2参照)に沿う断面を示し、図の右側に、Y方向に沿う断面を示している。また、図では各フィンの側面を垂直に示すが、フィンの側面は半導体基板の主面に対してテーパーを有していてもよい。
以下に、図33〜図35に示す比較例を参照して、本実施の形態の半導体装置の効果について説明する。図33〜図35のそれぞれは、比較例である半導体装置の断面図である。図33〜図35のそれぞれは、図4に示す断面と対応する位置での断面を示すものであり、フィンの長手方向に沿うメモリセルの断面と、フィンの短手方向に沿うメモリセルの断面とを示すものである。
以下に、図27を用いて、本実施の形態の半導体装置の変形例について説明する。図27は、本実施の形態の変形例である半導体装置を示す断面図である。図27では、メモリゲート電極への給電部の断面を示している。図27は、フィンの短手方向に沿う断面を示すものである。本変形例と、図1〜図24を用いて説明した半導体装置とは、メモリゲート電極へ接続されるプラグの態様のみ異なっている。
メモリゲート電極を構成するポリシリコン膜の上面は、シリサイド化することも可能である。以下では、図28〜図30を用いて、本実施の形態2の半導体装置およびその製造方法について説明する。図28〜図30は、本実施の形態の半導体装置の製造工程中の断面図である。図28〜図30のそれぞれは、図12〜図24に示す断面と対応する位置での断面を示すものであり、フィンの長手方向に沿うメモリセルの断面と、フィンの短手方向に沿うメモリセルの断面とを示すものである。ここでは、メモリゲート電極を構成するポリシリコン膜の上面をシリサイド化することについて説明する。
メモリゲート電極は、ポリシリコン膜と、当該ポリシリコン膜上の金属膜のみにより構成することもできる。以下では、図31および図32を用いて、本実施の形態3の半導体装置およびその製造方法について説明する。図31および図32は、本実施の形態の半導体装置の製造工程中の断面図である。図31および図32のそれぞれは、図12〜図24に示す断面と対応する位置での断面を示すものであり、フィンの長手方向に沿うメモリセルの断面と、フィンの短手方向に沿うメモリセルの断面とを示すものである。ここでは、メモリゲート電極をポリシリコン膜と当該ポリシリコン膜上の積層金属膜とにより構成することについて説明する。
D1 拡散領域
EI 素子分離膜
EX エクステンション領域
FA フィン
M1〜M3、MB 金属膜
MC メモリセル
MG、MG1〜MG3 メモリゲート電極
ON 絶縁膜(ONO膜)
PS1、PS2、PSB ポリシリコン膜
SB 半導体基板
Claims (10)
- 半導体基板と、
前記半導体基板の一部分であって、前記半導体基板の上面から突出し、前記半導体基板の前記上面に沿う第1方向に延在する突出部と、
前記突出部の上面上に第1絶縁膜を介して形成され、前記第1方向に直交する第2方向に延在する第1ゲート電極と、
前記突出部の前記上面上および前記突出部の側面上に電荷蓄積部を含む第2絶縁膜を介して形成され、前記第1ゲート電極の一方の側面に前記第2絶縁膜を介して隣り合い、前記第2方向に延在する第2ゲート電極と、
前記第1ゲート電極および前記第2ゲート電極からなるパターンの直下の前記突出部を前記第1方向において挟むように前記突出部の前記上面に形成された、ソース領域およびドレイン領域と、
を有し、
前記第1ゲート電極、前記第2ゲート電極、前記ソース領域および前記ドレイン領域は、不揮発性記憶素子を構成し、
前記第2ゲート電極は、前記第2絶縁膜上に順に形成された第1半導体膜、第1金属膜および第2半導体膜を有し、前記第2方向に隣り合う2つの前記突出部同士の間に前記第1半導体膜および前記第1金属膜が埋め込まれている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2方向に隣り合う2つの前記突出部同士の間に前記第2半導体膜が埋め込まれている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体膜の上面は、シリサイド層により覆われている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1半導体膜は、シリコン膜からなり、
前記第1金属膜は、窒化チタン膜からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記電荷蓄積部と前記第2ゲート電極との間には、酸化シリコン膜または酸化アルミニウム膜が介在している、半導体装置。 - 請求項1記載の半導体装置において、
前記第2ゲート電極の上面には、前記第1金属膜の上面が存在し、前記第1金属膜の前記上面にプラグが接続されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2半導体膜を貫通するプラグの底面が前記第1金属膜の上面に接続されている、半導体装置。 - (a)半導体基板を準備する工程、
(b)前記半導体基板の上面の一部を後退させることで、前記半導体基板の一部分であって、前記半導体基板の前記上面の前記一部から突出し、前記半導体基板の上面に沿う第1方向に延在する複数の突出部を形成する工程、
(c)隣り合う前記突出部同士の間の第1溝内を埋め込む素子分離膜を形成する工程、
(d)前記素子分離膜上において、前記突出部の上面および側面を第1絶縁膜を介して覆う第1ゲート電極を形成する工程、
(e)前記(d)工程の後、前記半導体基板上に電荷蓄積部である第2絶縁膜、第1半導体膜、第1金属膜および第2半導体膜を順に形成することで、前記第1方向に直交する第2方向に並ぶ前記突出部同士の間を、前記第1半導体膜、前記第1金属膜および第2半導体膜を含む積層膜により埋め込む工程、
(f)前記積層膜を加工することで、前記第1ゲート電極の一方の側面に前記第2絶縁膜を介して隣り合い、前記突出部の前記上面および前記側面を前記第2絶縁膜を介して覆う前記積層膜を含む第2ゲート電極を形成する工程、
(g)前記第1ゲート電極および前記第2ゲート電極からなるパターンの横の前記突出部の表面にソース・ドレイン領域を形成する工程、
を有する、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
(h)前記(g)工程の後、前記第2半導体膜の上面をシリサイド化する工程をさらに有する、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
(h)前記(g)工程の後、前記第2半導体膜を除去することで前記第2絶縁膜上に第2溝を形成する工程、
(i)前記(h)工程の後、前記第2溝内に第2金属膜を埋め込む工程、
をさらに有する、半導体装置の製造方法。
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