CN116110975A - 半浮栅存储器件及制备方法 - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 114
- 229920005591 polysilicon Polymers 0.000 claims abstract description 108
- 239000002184 metal Substances 0.000 claims abstract description 85
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 43
- 239000010703 silicon Substances 0.000 claims abstract description 43
- 238000005468 ion implantation Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000005498 polishing Methods 0.000 claims description 9
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 claims description 6
- 229910003855 HfAlO Inorganic materials 0.000 claims description 6
- 229910004143 HfON Inorganic materials 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- 229910006252 ZrON Inorganic materials 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 12
- 230000009977 dual effect Effects 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
本发明公开了一种半浮栅存储器件,为高K/金属栅极与氧化硅/多晶硅栅极共存的双控制栅半浮栅存储器件,其由外延生长结构形成控制栅外延硅层、源区及漏区,不需要单独进行源漏离子注入,节省了源漏离子注入所需要的光罩,制备成本低。本发明公开了所述半浮栅存储器件的制备方法。
Description
技术领域
本发明涉及集成电路制造技术,特别是涉及一种半浮栅存储器件及制备方法。
背景技术
伴随半导体器件尺寸不断缩小到28nm及以下工艺节点,晶体管栅极介质层SiON的厚度降低到2nm以下,导致晶体管器件的漏电流增大,半导体业界利用高K(介电常数)介质材料HfO2等取代SiON作为栅氧化层来减小栅介质层的量子隧穿效应,从而有效的改善晶体管栅极漏电流及其引起的功耗。
半浮栅存储器件是动态随机存储器(dynamic random access memory,DRAM)的替代概念,不同于通常的1T1C结构,半浮栅存储器件由一个浮栅晶体管、嵌入式隧穿晶体管和一个PN节组成,通过嵌入式隧穿晶体管的沟道和PN结对浮栅晶体管的浮栅进行写入和擦除操作。也有将控制栅的氧化物/多晶硅栅换成高K/金属栅来降低栅极漏电。
现有的半浮栅存储器件结构如图1所示,在具有第一掺杂类型的硅衬底100上形成有第二掺杂类型的半浮栅阱区101;在半浮栅阱区101形成一连通至硅衬底100的U型槽102;
浮栅多晶硅层103填充到所述U型槽102中及覆盖于U型槽102周边的半浮栅阱区101上方;
填充到所述U型槽102中的浮栅多晶硅层103同半浮栅阱区101之间有浮栅介质层104隔离;
覆盖于U型槽102周边的半浮栅阱区101上方的浮栅多晶硅层103,同半浮栅阱区101上表面之间有浮栅介质层104隔离,并通过覆盖在U型槽102左侧的半浮栅阱区101上表面的浮栅介质层104的一开口与半浮栅阱区101连通接触;,
浮栅介质层104和浮栅多晶硅层103共同构成浮栅叠层;
控制栅多晶硅105位于浮栅多晶硅层103上并从浮栅多晶硅层103的左侧下探到半浮栅阱区101上方,控制栅多晶硅105同浮栅多晶硅层103及半浮栅阱区101之间有介质层隔离;
在控制栅多晶硅105的下探部分左侧及控制栅多晶硅105、浮栅多晶硅层103的右侧分别形成有侧墙106;
在左侧墙左侧及右侧墙右侧的半浮栅阱区101分别注入离子形成源区107和漏区108。
现有的半浮栅存储器件,源漏离子注入需要单独的光罩,成本高。
发明内容
本发明要解决的技术问题是提供一种半浮栅晶体管及其制备方法,具有外延生长结构,能节省源漏离子注入所需要的光罩,制备成本低。
为解决上述技术问题,本发明提供的半浮栅存储器件,在具有第一掺杂类型的硅衬底100上形成有第二掺杂类型的半浮栅阱区101;第一掺杂类型为P型,第二掺杂类型为N型;或者,第一掺杂类型为N型,第二掺杂类型为P型;
在半浮栅阱区101形成一连通至硅衬底100的U型槽102;
第一掺杂类型的浮栅多晶硅层103填充到所述U型槽102中及覆盖于U型槽102周边的半浮栅阱区101上方;
填充到所述U型槽102中的浮栅多晶硅层103同半浮栅阱区101之间由浮栅介质层104隔离;
覆盖于U型槽102周边的半浮栅阱区101上方的浮栅多晶硅层103,同半浮栅阱区101上表面之间有浮栅介质层104隔离,并通过覆盖在U型槽102左侧的半浮栅阱区101上表面的浮栅介质层104的一开口与半浮栅阱区101连通接触;
控制栅氧化层110覆盖在浮栅多晶硅层103上表面;
控制栅多晶硅层111覆盖在控制栅氧化层110上表面;
金属栅113位于控制栅多晶硅层111左部上并从控制栅多晶硅层111的左侧下探到半浮栅阱区101上方,金属栅113同控制栅多晶硅层111及半浮栅阱区101之间由高K介质层112隔离;
在金属栅113的下探部分左侧、金属栅113位于控制栅多晶硅层111上方部分右侧、控制栅多晶硅层111及浮栅多晶硅层103均形成有侧墙106;
金属栅113左侧墙外的半浮栅阱区101及控制栅多晶硅层111右侧墙外的半浮栅阱区101上分别硅外延生长形成有源区107及漏区108;
控制栅多晶硅层111上硅外延生长形成有控制栅外延硅层114。
较佳的,控制栅外延硅层114低于金属栅113上表面。
较佳的,金属栅113下探到半浮栅阱区101上方的宽度为1~100nm;
覆盖在控制栅多晶硅层111上的金属栅113宽度为1~100nm。
较佳的,未被金属栅113覆盖的控制栅多晶硅层111的宽度为1~100nm;
控制栅外延硅层114的区域宽度为1~100nm;
硅外延生长形成的源区107及漏区108的宽度均为1~100nm。
较佳的,所述高K栅介质层112为ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON之一种,或其中任意几种的组合;
所述金属栅113为TiN、TaN、MoN、WN、TaC或TaCN之一种,或其中任意几种的组合。
为解决上述技术问题,本发明提供的半浮栅存储器件的制备方法,包括以下步骤:
S1.在第一掺杂类型的硅衬底100上形成第二掺杂类型的半浮栅阱区101,并刻蚀半浮栅阱区101形成连通到硅衬底100的U型槽102;第一掺杂类型为P型,第二掺杂类型为N型;或者,第一掺杂类型为N型,第二掺杂类型为P型;
S2.在U型槽102表面及半浮栅阱区101上表面形成浮栅介质层104;
S3.刻蚀所述浮栅介质层104,在U型槽103左侧的浮栅介质层104形成连通到半浮栅阱区101的开口105,暴露部分半浮栅阱区101;
S4.沉积浮栅多晶硅层103,进行第一掺杂类型离子注入并退火激活;
S5.在浮栅多晶硅103上沉积控制栅氧化层110和控制栅多晶硅层111;
S6.将所述开口左侧第一设定距离的之外的一段控制栅多晶硅层111、控制栅氧化层110和浮栅多晶硅层103、浮栅介质层104的上下叠层刻蚀去除,停止在半浮栅阱区101;
S7.在晶圆上形成高K介质层112;
S8.在所述高K介质层112上沉积金属栅113;
S9.进行金属栅113化学机械抛光;
S10.刻蚀去除所述开口左侧第二设定距离的之外的一段金属栅113、高K介质层112上下叠层,停止在半浮栅阱区101,第二设定距离大于第一设定距离;并刻蚀去除所述开口左部的右侧的一段金属栅113、高K介质层112上下叠层,停止在控制栅多晶硅层111;
S11.刻蚀去除U型槽102右侧第三设定距离之外的一段控制栅多晶硅层111、控制栅氧化层110、浮栅多晶硅103、浮栅介质层104上下叠层,停止在半浮栅阱区101,形成完整的多晶硅控制栅;
S12.形成栅极侧墙106;
S13.同时在控制栅多晶硅层111、金属栅113左侧墙外的半浮栅阱区101及控制栅多晶硅层111右侧墙外的半浮栅阱区101上进行硅外延生长,分别形成控制栅外延硅层114、源区107及漏区108。
较佳的,S9中,进行金属栅113化学机械抛光时,停止的金属栅113高度高于高K介质层112。
较佳的,S9中,进行金属栅113化学机械抛光时,停止的金属栅113高度高于高K介质层112 0.1nm~50nm。
较佳的,S10中,第二设定距离比第一设定距离大1~100nm,即金属栅113下探到半浮栅阱区101上方的宽度为1~100nm。
较佳的,刻蚀去除所述开口左部的右侧的一段金属栅113、高K介质层112上下叠层后,覆盖在控制栅多晶硅层111上的金属栅113宽度为1~100nm。
较佳的,S11中,刻蚀去除U型槽102右侧第三设定距离之外的一段控制栅多晶硅层111、控制栅氧化层110、浮栅多晶硅103、浮栅介质层104上下叠层后,未被金属栅113覆盖的控制栅多晶硅层111的宽度为1~100nm。
较佳的,所述高K栅介质层112为ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON之一种,或其中任意几种的组合;
所述金属栅113为TiN、TaN、MoN、WN、TaC或TaCN之一种,或其中任意几种的组合。
本发明的半浮栅存储器件及制备方法,为高K/金属栅极与氧化硅/多晶硅栅极共存的双控制栅半浮栅存储器件,其由外延生长结构形成控制栅外延硅层114、源区107及漏区108,不需要单独进行源漏离子注入,节省了源漏离子注入所需要的光罩,制备成本低。
附图说明
为了更清楚地说明本发明的技术方案,下面对本发明所需要使用的附图作简单的介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是现有的半浮栅存储器件结构示意图。
图2是本发明的半浮栅存储器件的制备方法一实施例的形成半浮栅阱区示意图;
图3是本发明的半浮栅存储器件的制备方法一实施例的形成浮栅介质层示意图;
图4是本发明的半浮栅存储器件的制备方法一实施例的刻蚀浮栅介质层暴露部分半浮栅阱区示意图;
图5是本发明的半浮栅存储器件的制备方法一实施例的沉积浮栅多晶硅层示意图;
图6是本发明的半浮栅存储器件的制备方法一实施例的沉积控制栅氧化层和控制栅多晶硅层示意图;
图7是本发明的半浮栅存储器件的制备方法一实施例的刻蚀去除控制栅多晶硅层、控制栅氧化层和浮栅多晶硅层、浮栅介质层的上下叠层示意图;
图8是本发明的半浮栅存储器件的制备方法一实施例的形成高K介质层示意图;
图9是本发明的半浮栅存储器件的制备方法一实施例的沉积金属栅示意图;
图10是本发明的半浮栅存储器件的制备方法一实施例的金属栅化学机械抛光示意图;
图11是本发明的半浮栅存储器件的制备方法一实施例的刻蚀去除金属栅、高K介质层上下叠层示意图;
图12是本发明的半浮栅存储器件的制备方法一实施例的形成完整的多晶硅控制栅及侧墙示意图;
图13是本发明的半浮栅存储器件的制备方法一实施例的进行硅外延生长,分别形成控制栅外延硅层、源区及漏区示意图。
具体实施方式
下面将结合附图,对本发明中的技术方案进行清楚、完整的描述,显然,所描述的实施例是本发明的一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动的前提下所获得的所有其它实施例,都属于本发明保护的范围。
实施例一
一种半浮栅存储器件,如图13所示,在具有第一掺杂类型的硅衬底100上形成有第二掺杂类型的半浮栅阱区101;第一掺杂类型为P型,第二掺杂类型为N型;或者,第一掺杂类型为N型,第二掺杂类型为P型;
在半浮栅阱区101形成一连通至硅衬底100的U型槽102;
第一掺杂类型的浮栅多晶硅层103填充到所述U型槽102中及覆盖于U型槽102周边的半浮栅阱区101上方;
填充到所述U型槽102中的浮栅多晶硅层103同半浮栅阱区101之间由浮栅介质层104隔离;
覆盖于U型槽102周边的半浮栅阱区101上方的浮栅多晶硅层103,同半浮栅阱区101上表面之间有浮栅介质层104隔离,并通过覆盖在U型槽102左侧的半浮栅阱区101上表面的浮栅介质层104的一开口与半浮栅阱区101连通接触;
控制栅氧化层110覆盖在浮栅多晶硅层103上表面;
控制栅多晶硅层111覆盖在控制栅氧化层110上表面;
金属栅113位于控制栅多晶硅层111左部上并从控制栅多晶硅层111的左侧下探到半浮栅阱区101上方,金属栅113同控制栅多晶硅层111及半浮栅阱区101之间由高K介质层112隔离;
在金属栅113的下探部分左侧、金属栅113位于控制栅多晶硅层111上方部分右侧、控制栅多晶硅层111及浮栅多晶硅层103均形成有侧墙106;
金属栅113左侧墙外的半浮栅阱区101及控制栅多晶硅层111右侧墙外的半浮栅阱区101上分别硅外延生长形成有源区107及漏区108;
控制栅多晶硅层111上硅外延生长形成有控制栅外延硅层114。
实施例一的半浮栅存储器件,为高K/金属栅极与氧化硅/多晶硅栅极共存的双控制栅半浮栅存储器件,其由外延生长结构形成控制栅外延硅层114、源区107及漏区108,不需要单独进行源漏离子注入,节省了源漏离子注入所需要的光罩,制备成本低。
实施例二
基于实施例一的半浮栅存储器件,控制栅外延硅层114低于金属栅113上表面。
较佳的,金属栅113下探到半浮栅阱区101上方的宽度为1~100nm。
较佳的,覆盖在控制栅多晶硅层111上的金属栅113宽度为1~100nm。
较佳的,未被金属栅113覆盖的控制栅多晶硅层111的宽度为1~100nm,控制栅外延硅层114的区域宽度为1~100nm,硅外延生长形成的源区107及漏区108的宽度均为1~100nm,从而能够引出导线进行控制。
较佳的,所述高K栅介质层112为ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON之一种,或其中任意几种的组合。
较佳的,所述金属栅113为TiN、TaN、MoN、WN、TaC或TaCN之一种,或其中任意几种的组合。
实施例三
一种实施例一或2的半浮栅存储器件的制备方法,包括以下步骤:
S1.在第一掺杂类型的硅衬底100上形成第二掺杂类型的半浮栅阱区101,并刻蚀半浮栅阱区101形成连通到硅衬底100的U型槽102;第一掺杂类型为P型,第二掺杂类型为N型;或者,第一掺杂类型为N型,第二掺杂类型为P型,如图2所示;
S2.在U型槽102表面及半浮栅阱区101上表面形成浮栅介质层104,如图3所示;
S3.刻蚀所述浮栅介质层104,在U型槽103左侧的浮栅介质层104形成连通到半浮栅阱区101的开口105,暴露部分半浮栅阱区101,如图4所示;
S4.沉积浮栅多晶硅层103,进行第一掺杂类型离子注入并退火激活,如图5所示;
S5.在浮栅多晶硅103上沉积控制栅氧化层110和控制栅多晶硅层111,如图6所示;
S6.将所述开口左侧第一设定距离的之外的一段控制栅多晶硅层111、控制栅氧化层110和浮栅多晶硅层103、浮栅介质层104的上下叠层刻蚀去除,停止在半浮栅阱区101,如图7所示;
S7.在晶圆上形成高K介质层112,如图8所示;
S8.在所述高K介质层112上沉积金属栅113,如图9所示;
S9.进行金属栅113化学机械抛光(CMP),如图10所示;
S10.刻蚀去除所述开口左侧第二设定距离的之外的一段金属栅113、高K介质层112上下叠层,停止在半浮栅阱区101,第二设定距离大于第一设定距离;并刻蚀去除所述开口左部的右侧的一段金属栅113、高K介质层112上下叠层,停止在控制栅多晶硅层111,如图11所示;
S11.刻蚀去除U型槽102右侧第三设定距离之外的一段控制栅多晶硅层111、控制栅氧化层110、浮栅多晶硅103、浮栅介质层104上下叠层,停止在半浮栅阱区101,形成完整的多晶硅控制栅;
S12.形成栅极侧墙106,如图12所示;
S13.同时在控制栅多晶硅层111、金属栅113左侧墙外的半浮栅阱区101及控制栅多晶硅层111右侧墙外的半浮栅阱区101上进行硅外延生长,分别形成控制栅外延硅层114、源区107及漏区108,如图13所示。
实施例三的半浮栅存储器件的制备方法,能制备高K/金属栅极与氧化硅/多晶硅栅极共存的双控制栅半浮栅存储器件,制备的半浮栅存储器件由外延生长结构形成控制栅外延硅层114、源区107及漏区108,不需要单独进行源漏离子注入,减少源漏离子注入减少了源漏离子注入所需要的光罩,节约成本。
实施例四
基于实施例三的半浮栅存储器件的制备方法,S9中,进行金属栅113化学机械抛光(CMP)时,停止的金属栅113高度高于高K介质层112。
较佳的,S9中,进行金属栅113化学机械抛光(CMP)时,停止的金属栅113高度高于高K介质层112在0.1nm~50nm。
较佳的,S10中,第二设定距离比第一设定距离大1~100nm,即金属栅113下探到半浮栅阱区101上方的宽度为1~100nm;
刻蚀去除所述开口左部的右侧的一段金属栅113、高K介质层112上下叠层后,覆盖在控制栅多晶硅层111上的金属栅113宽度为1~100nm。
较佳的,S11中,刻蚀去除U型槽102右侧第三设定距离之外的一段控制栅多晶硅层111、控制栅氧化层110、浮栅多晶硅103、浮栅介质层104上下叠层后,未被金属栅113覆盖的控制栅多晶硅层111的宽度为1~100nm。
较佳的,所述高K栅介质层112为ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON之一种,或其中任意几种的组合;
所述金属栅113为TiN、TaN、MoN、WN、TaC或TaCN之一种,或其中任意几种的组合。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明保护的范围之内。
Claims (12)
1.一种半浮栅存储器件,在具有第一掺杂类型的硅衬底(100)上形成有第二掺杂类型的半浮栅阱区(101);第一掺杂类型为P型,第二掺杂类型为N型;或者,第一掺杂类型为N型,第二掺杂类型为P型;其特征在于,在半浮栅阱区(101)形成一连通至硅衬底(100)的U型槽(102);
第一掺杂类型的浮栅多晶硅层(103)填充到所述U型槽(102)中及覆盖于U型槽(102)周边的半浮栅阱区(101)上方;
填充到所述U型槽(102)中的浮栅多晶硅层(103)同半浮栅阱区(101)之间由浮栅介质层(104)隔离;
覆盖于U型槽(102)周边的半浮栅阱区(101)上方的浮栅多晶硅层(103),同半浮栅阱区(101)上表面之间有浮栅介质层(104)隔离,并通过覆盖在U型槽(102)左侧的半浮栅阱区(101)上表面的浮栅介质层(104)的一开口与半浮栅阱区(101)连通接触;
控制栅氧化层(110)覆盖在浮栅多晶硅层(103)上表面;
控制栅多晶硅层(111)覆盖在控制栅氧化层(110)上表面;
金属栅(113)位于控制栅多晶硅层(111)左部上并从控制栅多晶硅层(111)的左侧下探到半浮栅阱区(101)上方,金属栅(113)同控制栅多晶硅层(111)及半浮栅阱区(101)之间由高K介质层(112)隔离;
在金属栅(113)的下探部分左侧、金属栅(113)位于控制栅多晶硅层(111)上方部分右侧、控制栅多晶硅层(111)及浮栅多晶硅层(103)均形成有侧墙(106);
金属栅(113)左侧墙外的半浮栅阱区(101)及控制栅多晶硅层(111)右侧墙外的半浮栅阱区(101)上分别硅外延生长形成有源区(107)及漏区(108);
控制栅多晶硅层(111)上硅外延生长形成有控制栅外延硅层(114)。
2.根据权利要求1所述的半浮栅存储器件,其特征在于,
控制栅外延硅层(114)低于金属栅(113)上表面。
3.根据权利要求1所述的半浮栅存储器件,其特征在于,
金属栅(113)下探到半浮栅阱区(101)上方的宽度为1~100nm;
覆盖在控制栅多晶硅层(111)上的金属栅(113)宽度为1~100nm。
4.根据权利要求1所述的半浮栅存储器件,其特征在于,
未被金属栅(113)覆盖的控制栅多晶硅层(111)的宽度为1~100nm;
控制栅外延硅层(114)的区域宽度为1~100nm;
硅外延生长形成的源区(107)及漏区(108)的宽度均为1~100nm。
5.根据权利要求1所述的半浮栅存储器件,其特征在于,
所述高K栅介质层(112)为ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON之一种,或其中任意几种的组合;
所述金属栅(113)为TiN、TaN、MoN、WN、TaC或TaCN之一种,或其中任意几种的组合。
6.一种权利要求1到4任一项半浮栅存储器件的制备方法,其特征在于,包括以下步骤:
S1.在第一掺杂类型的硅衬底(100)上形成第二掺杂类型的半浮栅阱区(101),并刻蚀半浮栅阱区(101)形成连通到硅衬底(100)的U型槽(102);第一掺杂类型为P型,第二掺杂类型为N型;或者,第一掺杂类型为N型,第二掺杂类型为P型;
S2.在U型槽(102)表面及半浮栅阱区(101)上表面形成浮栅介质层(104);
S3.刻蚀所述浮栅介质层(104),在U型槽(103)左侧的浮栅介质层(104)形成连通到半浮栅阱区(101)的开口(105),暴露部分半浮栅阱区(101);
S4.沉积浮栅多晶硅层(103),进行第一掺杂类型离子注入并退火激活;
S5.在浮栅多晶硅(103)上沉积控制栅氧化层(110)和控制栅多晶硅层(111);
S6.将所述开口左侧第一设定距离的之外的一段控制栅多晶硅层(111)、控制栅氧化层(110)和浮栅多晶硅层(103)、浮栅介质层(104)的上下叠层刻蚀去除,停止在半浮栅阱区(101);
S7.在晶圆上形成高K介质层(112);
S8.在所述高K介质层(112)上沉积金属栅(113);
S9.进行金属栅(113)化学机械抛光;
S10.刻蚀去除所述开口左侧第二设定距离的之外的一段金属栅(113)、高K介质层(112)上下叠层,停止在半浮栅阱区(101),第二设定距离大于第一设定距离;并刻蚀去除所述开口左部的右侧的一段金属栅(113)、高K介质层(112)上下叠层,停止在控制栅多晶硅层(111);
S11.刻蚀去除U型槽(102)右侧第三设定距离之外的一段控制栅多晶硅层(111)、控制栅氧化层(110)、浮栅多晶硅(103)、浮栅介质层(104)上下叠层,停止在半浮栅阱区(101),形成完整的多晶硅控制栅;
S12.形成栅极侧墙(106);
S13.同时在控制栅多晶硅层(111)、金属栅(113)左侧墙外的半浮栅阱区(101)及控制栅多晶硅层(111)右侧墙外的半浮栅阱区(101)上进行硅外延生长,分别形成控制栅外延硅层(114)、源区(107)及漏区(108)。
7.根据权利要求6所述的半浮栅存储器件的制备方法,其特征在于,
S9中,进行金属栅(113)化学机械抛光时,停止的金属栅(113)高度高于高K介质层(112)。
8.根据权利要求6所述的半浮栅存储器件的制备方法,其特征在于,
S9中,进行金属栅(113)化学机械抛光时,停止的金属栅(113)高度高于高K介质层(112)0.1nm~50nm。
9.根据权利要求6所述的半浮栅存储器件的制备方法,其特征在于,
S10中,第二设定距离比第一设定距离大1~100nm,即金属栅(113)下探到半浮栅阱区(101)上方的宽度为1~100nm。
10.根据权利要求6所述的半浮栅存储器件的制备方法,其特征在于,
刻蚀去除所述开口左部的右侧的一段金属栅(113)、高K介质层(112)上下叠层后,覆盖在控制栅多晶硅层(111)上的金属栅(113)宽度为1~100nm。
11.根据权利要求6所述的半浮栅存储器件的制备方法,其特征在于,
S11中,刻蚀去除U型槽(102)右侧第三设定距离之外的一段控制栅多晶硅层(111)、控制栅氧化层(110)、浮栅多晶硅(103)、浮栅介质层(104)上下叠层后,未被金属栅(113)覆盖的控制栅多晶硅层(111)的宽度为1~100nm。
12.根据权利要求6所述的半浮栅存储器件的制备方法,其特征在于,
所述高K栅介质层(112)为ZrO2、ZrON、ZrSiON、HfZrO、HfZrON、HfON、HfO2、HfAlO、HfAlON、HfSiO、HfSiON、HfLaO、HfLaON之一种,或其中任意几种的组合;
所述金属栅(113)为TiN、TaN、MoN、WN、TaC或TaCN之一种,或其中任意几种的组合。
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