JP6652445B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6652445B2 JP6652445B2 JP2016095047A JP2016095047A JP6652445B2 JP 6652445 B2 JP6652445 B2 JP 6652445B2 JP 2016095047 A JP2016095047 A JP 2016095047A JP 2016095047 A JP2016095047 A JP 2016095047A JP 6652445 B2 JP6652445 B2 JP 6652445B2
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Description
本実施の形態1および以下の実施の形態の半導体装置は、不揮発性メモリ(不揮発性記憶素子、フラッシュメモリ、不揮発性半導体記憶装置)を備えた半導体装置である。本実施の形態および以下の実施の形態では、不揮発性メモリは、nチャネル型MISFET(MISFET:Metal Insulator Semiconductor Field Effect Transistor)を基本としたメモリセルをもとに説明を行う。
以下に、本実施の形態1による半導体装置の製造方法について図1〜図17を用いて工程順に説明する。図1〜図17は、本実施の形態による半導体装置の製造工程中の断面図である。
次に、不揮発性メモリの動作例について説明する。不揮発性メモリセルであるメモリセルMCの動作としては、書込み、消去および読出しがある。ここでは、書込みおよび消去の動作においてSSI(Source Side Injection)方式を用いる。本実施の形態では、ONO膜である絶縁膜CSL中の電荷蓄積部である窒化シリコン膜C2への電子の注入を「書込み」、電子の抜き出しを「消去」と定義する。
以下に、図28〜図30を用いて、比較例の半導体装置の製造方法について説明し、本実施の形態の半導体装置の製造方法の効果について説明する。図30は、制御ゲート電極のゲート長が比較的大きい場合の比較例2の半導体装置の製造工程中の断面図であり、図28および図29は、制御ゲート電極のゲート長が図30に示す構造よりも小さい場合の比較例1の半導体装置の製造工程中の断面図である。図28〜図30では、図1〜図17と同じように、メモリセル領域1A、低電圧MIS領域1Bおよび高電圧MIS領域1Cを示している。
以下に、図18および図19を用いて、本実施の形態の変形例である半導体装置の製造工程について説明する。図18および図19は、本実施の形態の変形例である半導体装置の製造工程中の断面図である。本変形例は、メモリセルのソース・ドレイン領域のそれぞれの拡散層を互いに別工程で形成する点で、図1〜図17を用いて説明した実施の形態と同様である。ただし、本変形例では、当該ソース・ドレイン領域のそれぞれの拡散層を同じ深さで形成し、互いに異なる濃度とする点で、図1〜図17を用いて説明した工程と異なる。
以下に、メモリセルのドレイン領域を構成する拡散層と、低電圧MISおよび高電圧MISのそれぞれのソース・ドレイン領域を構成する拡散層とを同一のイオン注入工程により形成する場合について、図20〜図22を用いて説明する。図20〜図22は、本実施の形態2の半導体装置の製造工程中の断面図である。図20〜図22では、図1〜図17と同様に、メモリセル領域1A、低電圧MIS領域1Bおよび高電圧MIS領域1Cを示している。
以下に、メモリセルの制御ゲート電極側(ドレイン領域側)のサイドウォールを、メモリゲート電極側のサイドウォールよりも小さい幅で形成することについて、図23〜図27を用いて説明する。図23〜図27は、本実施の形態3の半導体装置の製造工程中の断面図である。図23〜図27では、図1〜図17と同様に、メモリセル領域1A、低電圧MIS領域1Bおよび高電圧MIS領域1Cを示している。
1B 低電圧MIS領域
1C 高電圧MIS領域
CG 制御ゲート電極
CH1 チャネル領域
CSL 絶縁膜
DL1〜DL3 拡散層
DR1、DR2、HR 拡散領域
EX1〜EX4 エクステンション領域
GE1、GE2 ゲート電極
HL1、HL2 ハロー領域
MC メモリセル
MG メモリゲート電極
Q1 低電圧MIS
Q2 高電圧MIS
SB 半導体基板
Claims (11)
- (a)表面に第1導電型の第1半導体領域を備えた半導体基板を用意する工程、
(b)前記半導体基板上に、第1絶縁膜を介して第1ゲート電極を形成する工程、
(c)前記第1ゲート電極の第1側壁に、内部に電荷蓄積部を有する第2絶縁膜を介して隣接する第2ゲート電極を、前記半導体基板上に前記第2絶縁膜を介して形成する工程、
(d)前記第1ゲート電極の前記第1側壁の反対側の第2側壁に隣接する第1領域の前記半導体基板の上面に、前記第1導電型の第2半導体領域を形成する工程、
(c1)前記(c)工程の後、前記第1領域の前記半導体基板の前記上面に、前記第1導電型と異なる第2導電型の不純物を導入することで第3半導体領域を形成する工程、
(c2)前記(c)工程の後、前記第1ゲート電極側の反対側の前記第2ゲート電極の第3側壁に隣接する第2領域の前記半導体基板の前記上面に、前記第2導電型の不純物を導入することで第4半導体領域を形成する工程、
(e)前記(c1)および前記(c2)工程の後、前記第1領域の前記半導体基板の前記上面に、前記第2導電型の不純物を導入することで、第1拡散層を形成する工程、
(f)前記(c1)および前記(c2)工程の後、前記第2領域の前記半導体基板の前記上面に、前記第2導電型の不純物を導入することで、前記第1拡散層よりも深い第2拡散層を形成する工程、
(g)前記(d)工程、前記(e)工程および前記(f)工程のうち、最後に行う工程の後、前記半導体基板を加熱する工程、
を有し、
前記(g)工程では、加熱により前記第1拡散層および前記第2拡散層のそれぞれの内部の前記第2導電型の不純物を拡散させて、前記半導体基板内において、前記第1拡散層を覆う前記第2導電型の第1拡散領域と、前記第2拡散層を覆う前記第2導電型の第2拡散領域とを形成し、
前記第1拡散層を含むドレイン領域、前記第2拡散層を含むソース領域、前記第1ゲート電極および前記第2ゲート電極は、不揮発性メモリのメモリセルを構成し、
前記第3半導体領域の前記第2導電型の不純物濃度は、前記第1拡散層の前記第2導電型の不純物濃度よりも低く、
前記第4半導体領域の前記第2導電型の不純物濃度は、前記第2拡散層の前記第2導電型の不純物濃度よりも低く、
前記半導体基板の主面において、前記第2拡散領域は、前記第4半導体領域よりも前記第1拡散層側に位置する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第2拡散層の前記第2導電型の不純物濃度は、前記第1拡散層の前記第2導電型の不純物濃度より高い、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記半導体基板の前記主面において、前記第1拡散領域の前記第2拡散領域側の端部は、前記第3半導体領域の前記第2拡散領域側の端部よりも前記第1拡散層側に位置する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第4半導体領域は、前記第2拡散領域および前記第2拡散層に覆われている、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
(d1)前記(c1)工程および前記(c2)工程のうち、最後に行う工程の後、前記(e)工程および前記(f)工程のうち、最初に行う工程の前に、前記第2側壁を覆う第1サイドウォールと、前記第3側壁を覆う第2サイドウォールとを形成する工程をさらに有する、半導体装置の製造方法。 - 請求項5記載の半導体装置の製造方法において、
前記第1ゲート電極のゲート長方向の前記第1サイドウォールの幅は、前記ゲート長方向の前記第2サイドウォールの幅よりも小さい、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
(c3)前記(d)工程の前に、前記半導体基板上に第3絶縁膜を介して第3ゲート電極を形成し、
(e1)前記(g)工程の前に、前記第3ゲート電極の横の前記半導体基板の前記上面に、前記第2導電型の不純物を導入することで、一対の第3拡散層を形成する工程、
をさらに有し、
一対の前記第3拡散層および前記第3ゲート電極は、電界効果トランジスタを構成する、半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記第3拡散層の前記第2導電型の不純物濃度は、前記第1拡散層の前記第2導電型の不純物濃度よりも高い、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
(c3)前記(d)工程の前に、前記半導体基板上に第3絶縁膜を介して第3ゲート電極を形成する工程をさらに有し、
前記(e)工程では、前記第1領域の前記半導体基板の前記上面と、前記第3ゲート電極の横の前記半導体基板の前記上面とに、前記第2導電型の不純物を導入することで、前記第1拡散層と、前記第3ゲート電極の横の一対の第3拡散層を形成し、
一対の前記第3拡散層および前記第3ゲート電極は、電界効果トランジスタを構成する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第2半導体領域と前記第2拡散領域とは、互いに接している、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1拡散領域と前記第1ゲート電極とは、平面視において互いに離間している、半導体装置の製造方法。
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