JP5404149B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP5404149B2 JP5404149B2 JP2009100055A JP2009100055A JP5404149B2 JP 5404149 B2 JP5404149 B2 JP 5404149B2 JP 2009100055 A JP2009100055 A JP 2009100055A JP 2009100055 A JP2009100055 A JP 2009100055A JP 5404149 B2 JP5404149 B2 JP 5404149B2
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- gate electrode
- select gate
- insulating film
- control gate
- impurity region
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- 239000004065 semiconductor Substances 0.000 title claims description 37
- 239000012535 impurity Substances 0.000 claims description 106
- 239000000758 substrate Substances 0.000 claims description 31
- 238000002955 isolation Methods 0.000 claims description 24
- 230000002093 peripheral effect Effects 0.000 claims description 13
- 239000011229 interlayer Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 239000010410 layer Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 238000000206 photolithography Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Description
本発明の実施形態1に係る半導体記憶装置において、前記第1コントロールゲート電極は、接地配線と電気的に接続され、前記第2コントロールゲート電極は、電圧制御される配線に電気的に接続されていることが好ましい。
本発明の実施形態2に係る半導体記憶装置の製造方法において前記セレクトゲート電極及び前記第1、第2不純物領域の表面を露出させる工程の後、前記第1、第2不純物領域、前記セレクトゲート電極及び前記第1、第2コントロールゲート電極を含む前記基板上に層間絶縁膜を成膜する工程と、前記層間絶縁膜の所定の位置に前記第1、第2不純物領域、前記セレクトゲート電極及び前記第1、第2コントロールゲート電極に通ずる下穴を形成する工程と、前記下穴にビアを埋め込む工程と、前記ビアを含む前記層間絶縁膜上の所定の位置にビット線、ワード線を含む配線を形成する工程と、を含むことが好ましい。
2a 不純物領域(第1不純物領域)
2b 不純物領域(第2不純物領域)
3 ゲート絶縁膜
4 セレクトゲート電極
5 ゲート分離絶縁膜
6a コントロールゲート電極(第1コントロールゲート電極)
6b コントロールゲート電極(第2コントロールゲート電極)
8 層間絶縁膜
9 ビア
101 基板
102a、102b 不純物領域
103 ゲート絶縁膜
104 セレクトゲート電極
105 ゲート分離絶縁膜
106 シリコン層
106a、106b コントロールゲート電極
107 レジスト
107a 開口部
Claims (1)
- 基板のチャネル領域の両側に形成された第1、第2不純物領域と、
前記チャネル領域上にゲート絶縁膜を介して形成されたセレクトゲート電極と、
前記セレクトゲート電極の両側面乃至チャネル領域の表面にゲート分離絶縁膜を介してサイドウォール状に形成された第1、第2コントロールゲート電極と、
を有するメモリセルを備え、
前記メモリセルは、行方向及び列方向に並んで配され、
前記第2不純物領域は、列方向に隣り合う前記第2不純物領域同士が繋がるように構成されるとともに、共通ソース線と電気的に接続され、
前記セレクトゲート電極は、前記第2不純物領域を囲むようにリング状に構成されるとともに、ワード線と電気的に接続され、
前記第1コントロールゲート電極は、前記セレクトゲート電極の外周側にてリング状に構成され、
前記第2コントロールゲート電極は、前記セレクトゲート電極の内周側であって前記第2不純物領域の外周側にてリング状に構成され、
前記第1不純物領域は、前記第1コントロールゲート電極の外周側に配されるとともに、列方向に隣り合う前記第1不純物領域同士が繋がらないように構成され、
前記メモリセル上にて行ごとに対応する第1、第2ビット線が配され、
前記第1ビット線は、前記第2不純物領域を挟んで行方向に隣り合う第1不純物領域の一方と電気的に接続され、
前記第2ビット線は、前記第2不純物領域を挟んで行方向に隣り合う第1不純物領域の他方と電気的に接続されていることを特徴とする半導体記憶装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009100055A JP5404149B2 (ja) | 2009-04-16 | 2009-04-16 | 半導体記憶装置 |
US12/761,149 US8247858B2 (en) | 2009-04-16 | 2010-04-15 | Semiconductor storage device and method of manufacturing same |
CN201010163888.2A CN101866926B (zh) | 2009-04-16 | 2010-04-16 | 半导体存储装置及其制造方法 |
US13/551,240 US8912062B2 (en) | 2009-04-16 | 2012-07-17 | Semiconductor storage device and method of manufacturing same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009100055A JP5404149B2 (ja) | 2009-04-16 | 2009-04-16 | 半導体記憶装置 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013224507A Division JP5650303B2 (ja) | 2013-10-29 | 2013-10-29 | 半導体記憶装置の製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010251557A JP2010251557A (ja) | 2010-11-04 |
JP2010251557A5 JP2010251557A5 (ja) | 2012-05-10 |
JP5404149B2 true JP5404149B2 (ja) | 2014-01-29 |
Family
ID=42958566
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009100055A Active JP5404149B2 (ja) | 2009-04-16 | 2009-04-16 | 半導体記憶装置 |
Country Status (3)
Country | Link |
---|---|
US (2) | US8247858B2 (ja) |
JP (1) | JP5404149B2 (ja) |
CN (1) | CN101866926B (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101979299B1 (ko) * | 2012-12-26 | 2019-09-03 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 그 제조방법 |
CN103366810B (zh) * | 2013-07-26 | 2017-07-28 | 上海华虹宏力半导体制造有限公司 | Eeprom存储器阵列 |
JP6235901B2 (ja) * | 2013-12-27 | 2017-11-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR101824376B1 (ko) | 2014-10-15 | 2018-01-31 | 플로디아 코포레이션 | 반도체 장치 및 그 제조 방법 |
WO2016060012A1 (ja) * | 2014-10-15 | 2016-04-21 | 株式会社フローディア | 半導体集積回路装置の製造方法、および半導体集積回路装置 |
JP5905630B1 (ja) * | 2015-08-13 | 2016-04-20 | 株式会社フローディア | 半導体集積回路装置の製造方法、および半導体集積回路装置 |
US10074438B2 (en) * | 2016-06-10 | 2018-09-11 | Cypress Semiconductor Corporation | Methods and devices for reducing program disturb in non-volatile memory cell arrays |
CN109216466A (zh) * | 2017-07-05 | 2019-01-15 | 北京兆易创新科技股份有限公司 | 存储单元及存储器 |
JP7026537B2 (ja) * | 2018-03-07 | 2022-02-28 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
JP2021150592A (ja) * | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置 |
CN117295341A (zh) * | 2023-09-28 | 2023-12-26 | 北京大学 | 铁电非易失存储器及制备方法 |
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KR0125113B1 (ko) * | 1993-02-02 | 1997-12-11 | 모리시타 요이찌 | 불휘발성 반도체 메모리 집적장치 및 그 제조방법 |
US5427968A (en) * | 1994-04-13 | 1995-06-27 | United Microelectronics Corp. | Split-gate flash memory cell with separated and self-aligned tunneling regions |
DE19600307C1 (de) * | 1996-01-05 | 1998-01-08 | Siemens Ag | Hochintegrierter Halbleiterspeicher und Verfahren zur Herstellung des Halbleiterspeichers |
US5950087A (en) * | 1998-09-10 | 1999-09-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method to make self-aligned source etching available in split-gate flash |
US6204126B1 (en) * | 2000-02-18 | 2001-03-20 | Taiwan Semiconductor Manufacturing Company | Method to fabricate a new structure with multi-self-aligned for split-gate flash |
JP4904631B2 (ja) * | 2000-10-27 | 2012-03-28 | ソニー株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
DE60133619T2 (de) | 2000-12-05 | 2009-06-10 | Halo Lsi Design And Device Technology Inc. | Programmier- und Löschverfahren in Zwilling-MONOS-Zellenspeichern |
JP2002231829A (ja) | 2001-01-22 | 2002-08-16 | Halo Lsi Design & Device Technol Inc | 不揮発性半導体メモリおよびその製造方法 |
DE60231267D1 (de) * | 2001-03-26 | 2009-04-09 | Halo Lsi Design & Device Tech | Nebenschluss- und Auswahlimplementierung in einer MONOS-Zwillingsspeicherzellenmatrix |
US6518123B2 (en) * | 2001-06-14 | 2003-02-11 | Taiwan Semiconductor Manufacturing Co., Ltd | Split gate field effect transistor (FET) device with annular floating gate electrode and method for fabrication thereof |
ATE373862T1 (de) * | 2001-07-06 | 2007-10-15 | Halo Lsi Design & Device Tech | Steuergate- und wortleitungs- spannungserhöhungsverfahren für zwilling-monos- zellenspeichern |
US6670240B2 (en) * | 2001-08-13 | 2003-12-30 | Halo Lsi, Inc. | Twin NAND device structure, array operations and fabrication method |
JP2003218244A (ja) * | 2002-01-24 | 2003-07-31 | Seiko Epson Corp | 半導体装置の製造方法 |
US6624028B1 (en) * | 2002-03-04 | 2003-09-23 | Megawin Technology Co., Ltd. | Method of fabricating poly spacer gate structure |
US6838344B2 (en) * | 2002-03-12 | 2005-01-04 | Halo Lsi, Inc. | Simplified twin monos fabrication method with three extra masks to standard CMOS |
JP4647175B2 (ja) * | 2002-04-18 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
JP2003332472A (ja) * | 2002-05-16 | 2003-11-21 | Sony Corp | 不揮発性半導体メモリ装置およびその製造方法 |
US6746920B1 (en) * | 2003-01-07 | 2004-06-08 | Megawin Technology Co., Ltd. | Fabrication method of flash memory device with L-shaped floating gate |
JP2004342682A (ja) * | 2003-05-13 | 2004-12-02 | Sharp Corp | 半導体装置及びその製造方法、携帯電子機器、並びにicカード |
JP4629982B2 (ja) * | 2004-02-13 | 2011-02-09 | ルネサスエレクトロニクス株式会社 | 不揮発性記憶素子およびその製造方法 |
JP2005347589A (ja) * | 2004-06-04 | 2005-12-15 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置及びその製造方法 |
JP2006041354A (ja) * | 2004-07-29 | 2006-02-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7352033B2 (en) * | 2005-08-30 | 2008-04-01 | Halo Lsi Inc. | Twin MONOS array for high speed application |
-
2009
- 2009-04-16 JP JP2009100055A patent/JP5404149B2/ja active Active
-
2010
- 2010-04-15 US US12/761,149 patent/US8247858B2/en not_active Expired - Fee Related
- 2010-04-16 CN CN201010163888.2A patent/CN101866926B/zh active Active
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2012
- 2012-07-17 US US13/551,240 patent/US8912062B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US8247858B2 (en) | 2012-08-21 |
US20120329223A1 (en) | 2012-12-27 |
US8912062B2 (en) | 2014-12-16 |
US20100264483A1 (en) | 2010-10-21 |
CN101866926A (zh) | 2010-10-20 |
CN101866926B (zh) | 2014-12-03 |
JP2010251557A (ja) | 2010-11-04 |
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