JP7117223B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP7117223B2 JP7117223B2 JP2018210611A JP2018210611A JP7117223B2 JP 7117223 B2 JP7117223 B2 JP 7117223B2 JP 2018210611 A JP2018210611 A JP 2018210611A JP 2018210611 A JP2018210611 A JP 2018210611A JP 7117223 B2 JP7117223 B2 JP 7117223B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- manufacturing
- insulating film
- fins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 123
- 238000004519 manufacturing process Methods 0.000 title claims description 86
- 230000015654 memory Effects 0.000 claims description 121
- 238000002955 isolation Methods 0.000 claims description 113
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 85
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 84
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 80
- 229920005591 polysilicon Polymers 0.000 claims description 80
- 238000005530 etching Methods 0.000 claims description 72
- 238000000034 method Methods 0.000 claims description 58
- 230000015572 biosynthetic process Effects 0.000 claims description 49
- 239000000758 substrate Substances 0.000 claims description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 31
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 31
- 230000002093 peripheral effect Effects 0.000 claims description 27
- 125000006850 spacer group Chemical group 0.000 claims description 23
- 238000003860 storage Methods 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 230000005669 field effect Effects 0.000 description 37
- 101150055709 SNF1 gene Proteins 0.000 description 20
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 239000012535 impurity Substances 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 238000005036 potential barrier Methods 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 101000702559 Homo sapiens Probable global transcription activator SNF2L2 Proteins 0.000 description 5
- 101000702545 Homo sapiens Transcription activator BRG1 Proteins 0.000 description 5
- 102100031021 Probable global transcription activator SNF2L2 Human genes 0.000 description 5
- 239000002784 hot electron Substances 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- 239000010410 layer Substances 0.000 description 5
- 230000006872 improvement Effects 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000007687 exposure technique Methods 0.000 description 3
- 238000007654 immersion Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- JPKJQBJPBRLVTM-OSLIGDBKSA-N (2s)-2-amino-n-[(2s,3r)-3-hydroxy-1-[[(2s)-1-[[(2s)-1-[[(2s)-1-[[(2r)-1-(1h-indol-3-yl)-3-oxopropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxo-3-phenylpropan-2-yl]amino]-1-oxobutan-2-yl]-6-iminohexanamide Chemical compound C([C@H](NC(=O)[C@@H](NC(=O)[C@@H](N)CCCC=N)[C@H](O)C)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@@H](CC=1C=CC=CC=1)C(=O)N[C@H](CC=1C2=CC=CC=C2NC=1)C=O)C1=CC=CC=C1 JPKJQBJPBRLVTM-OSLIGDBKSA-N 0.000 description 2
- 102100031277 Calcineurin B homologous protein 1 Human genes 0.000 description 2
- 241000839426 Chlamydia virus Chp1 Species 0.000 description 2
- 101000777252 Homo sapiens Calcineurin B homologous protein 1 Proteins 0.000 description 2
- 101000943802 Homo sapiens Cysteine and histidine-rich domain-containing protein 1 Proteins 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- -1 Metal Oxide Nitride Chemical class 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000004335 scaling law Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
- H01L29/42352—Gate electrodes for transistors with charge trapping gate insulator with the gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
Description
例えば、集積回路などに使用される電界効果トランジスタにおいては、性能の向上や製造コストの低減の観点から、スケーリング則にしたがって、寸法の微細化が進められてきている。ところが、電界効果トランジスタの寸法の縮小化が進むにつれて、電界効果トランジスタの加工に使用される露光技術の開発が困難となってきており、電界効果トランジスタの加工に使用される半導体製造装置(加工装置)の価格が非常に高価となっている。
図1は、関連技術における半導体装置のフィン構造を模式的に示す図である。
図10は、「フィン構造」の電界効果トランジスタにおけるフィンの模式的なレイアウト構成を示す図である。図10において、フィンFAは、y方向に所定間隔で配置され、かつ、複数のフィンFAのそれぞれは、y方向と直交するx方向に延在している。
図12は、図11に示す領域R2に形成されている「フィン構造」の電界効果トランジスタの模式的な構成を示す斜視図である。図12に示すように、本実施の形態1における「フィン構造」の電界効果トランジスタは、半導体基板1Sを加工して形成されたフィンFAを有し、このフィンFAは、素子分離領域STIで挟まれている。そして、フィンFAと接する素子分離領域STIの表面には、凹部GV1が形成されている。この凹部GV1は、フィンFAが延在するx方向に沿って延在している。そして、本実施の形態1における「フィン構造」の電界効果トランジスタは、フィンFAを跨ぎ、かつ、y方向に延在するゲート電極GE1を有し、このゲート電極GE1の下層には、例えば、酸化シリコン膜からなるゲート絶縁膜GOXが形成されている。一方、ゲート電極GE1の両側側壁には、絶縁膜からなるサイドウォールスペーサSWが形成されている。このように構成されている「フィン構造」の電界効果トランジスタによれば、素子分離領域STIから突出したフィンFAの上面と側面とを覆うように、ゲート絶縁膜GOXを介してゲート電極GE1が形成されている。このため、「フィン構造」の電界効果トランジスタは、ゲート電極GE1で覆われているフィンFAの上面と側面とがチャネル形成領域として機能するため、フィンFAを有さない「プレーナ型」の電界効果トランジスタよりも、性能向上を図ることができる。
本実施の形態1における「フィン構造」の電界効果トランジスタは、上記のように構成されており、以下に、その製造方法について図面を参照しながら説明する。なお、製造工程を説明する図面では、図11のA-A線で切断した断面図を使用する。
続いて、本実施の形態1における製法上の特徴点について説明する。
次に、本実施の形態1における構造上の特徴点について説明する。
前記実施の形態1では、「フィン構造」の電界効果トランジスタを例に挙げて、前記実施の形態1における技術的思想を説明した。これに対し、本実施の形態2においては、メモリアレイ形成領域に形成されている「フィン構造」の不揮発性メモリセルと、周辺回路形成領域に形成されている「フィン構造」の電界効果トランジスタとを含む半導体装置に、前記実施の形態1における技術的思想を適用する例について説明する。
本実施の形態2における不揮発性メモリを有する半導体装置について説明する。
次に、本実施の形態2における不揮発性メモリのデバイス構造について説明する。
続いて、本実施の形態2における不揮発性メモリの動作について説明する。
次に、本実施の形態2における半導体装置の製造方法について説明する。
「フィン構造」を形成する際に素子分離領域STI上に段差が発生することを抑制する工夫点は、もちろん、前記実施の形態1における「フィン構造」の電界効果トランジスタの製造工程にも有用であるが、本実施の形態2における「フィン構造」のメモリセルを形成する際に特に有用である。なぜなら、本実施の形態2における「フィン構造」のメモリセルは、コントロールゲート電極CGの片側の側壁にサイドウォール形状のメモリゲート電極MGを形成した、いわゆる「スプリットゲート型メモリセル」であるからである。つまり、このメモリセルでは、メモリゲート電極MGの高さを確保するために、コントロールゲート電極CGの高さを高くする必要があり、このことは、コントロールゲート電極CGとなるポリシリコン膜PF1の膜厚を厚くする必要があることを意味している。そして、ポリシリコン膜PF1の膜厚が厚くなると、仮に段差が生じている領域が存在すると、その領域においてポリシリコン膜の膜厚が特に増大して、エッチング残渣が発生しやすくなるのである。したがって、本実施の形態2における「フィン構造」のメモリセルを形成する際には、「フィン構造」を形成する際に生じる段差を抑制する工夫が特に重要となる。このことから、「フィン構造」を形成する際に素子分離領域STI上に段差が発生することを抑制する工夫点は、特に、本実施の形態2において有用性が高まると言える。
CG コントロールゲート電極
DIT 素子分離溝
FA フィン
GOX ゲート絶縁膜
GV1 凹部
GV2 凹部
IF 積層絶縁膜
MG メモリゲート電極
OXF1 酸化シリコン膜
OXF2 酸化シリコン膜
OXF3 酸化シリコン膜
OXF4 酸化シリコン膜
PF1 ポリシリコン膜
PR1 レジストパターン
PR2 レジストパターン
R1 メモリアレイ形成領域
R2 境界領域
R3 周辺回路形成領域
SNF1 窒化シリコン膜
SNF2 窒化シリコン膜
STI 素子分離領域
SW サイドウォールスペーサ
Claims (10)
- (a)半導体基板を加工することにより、第1方向に所定間隔で配置され、かつ、前記第1方向と直交する第2方向にそれぞれ延在する複数のフィンと、平面視において前記複数のフィンを内包する素子分離溝を形成する工程、
(b)前記素子分離溝に絶縁膜を埋め込む工程、
(c)平面視において、前記素子分離溝に内包され、かつ、前記複数のフィン全体を囲むパターンを前記絶縁膜上に形成する工程、
(d)前記パターンをマスクにしたエッチングにより、前記パターンから露出する前記絶縁膜の膜厚を減じる工程、
を備える、半導体装置の製造方法であって、
前記(c)工程では、前記複数のフィンのうちの前記第1方向において最も外側に配置されている第1フィンと前記パターンとの間の距離は、前記所定間隔以下であり、かつ、前記複数のフィンのそれぞれの前記第2方向における端部と前記パターンとの間の距離も、前記所定間隔以下であり、
前記半導体装置の製造方法は、さらに、
(e)前記複数のフィンのそれぞれの表面にゲート絶縁膜を形成する工程、
(f)前記表面にそれぞれ前記ゲート絶縁膜を形成した前記複数のフィンと、前記絶縁膜とを覆う第1導体膜を形成する工程、
(g)前記第1導体膜をパターニングすることにより、前記第1方向に延在する複数のゲート電極を形成する工程、
を有し、
前記複数のフィンのそれぞれの前記第2方向における端部と前記パターンとの間の距離は、互いに隣り合うゲート電極の間の距離以上である、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(d)工程では、前記絶縁膜の表面に凸形状が形成される、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記複数のフィンが形成されている領域は、複数のメモリセルが形成されるメモリアレイ形成領域であり、
前記素子分離溝の外側領域は、周辺回路形成領域である、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
平面視において、前記素子分離溝は、
前記複数のフィンが形成されているアレイ形成領域と、
前記アレイ形成領域の外側に形成されている給電部と、
を内包している、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記(d)工程では、等方性エッチングを使用し、
前記(c)工程では、前記複数のフィンのうちの前記第1方向において最も外側に配置されている第1フィンと前記パターンとの間の距離は、前記所定間隔よりも小さく、かつ、前記複数のフィンのそれぞれの前記第2方向における端部と前記パターンとの間の距離も、前記所定間隔よりも小さい、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記パターンは、レジストパターンである、半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記複数のゲート電極のそれぞれは、コントロールゲート電極であり、
前記半導体装置の製造方法は、さらに、
(h)前記コントロールゲート電極を覆う積層絶縁膜を形成する工程、
(i)前記積層絶縁膜上に第2導体膜を形成する工程、
(j)前記第2導体膜を異方性エッチングすることにより、前記積層絶縁膜を介した前記コントロールゲート電極の両側の側壁にサイドウォールスペーサを形成する工程、
(k)前記コントロールゲート電極の一方の側壁に形成されている前記サイドウォールスペーサを残す一方、前記コントロールゲート電極の他方の側壁に形成されている前記サイドウォールスペーサを除去することにより、前記コントロールゲート電極の一方の側壁に、前記サイドウォールスペーサからなるメモリゲート電極を形成する工程、
を有する、半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記(h)工程は、
(h1)前記コントロールゲート電極を覆う第1絶縁膜を形成する工程、
(h2)前記第1絶縁膜上に電荷蓄積膜を形成する工程、
(h3)前記電荷蓄積膜上に第2絶縁膜を形成する工程、
を含む、半導体装置の製造方法。 - 請求項8に記載の半導体装置の製造方法において、
前記第1絶縁膜は、酸化シリコン膜であり、
前記電荷蓄積膜は、窒化シリコン膜であり、
前記第2絶縁膜は、酸化シリコン膜である、半導体装置の製造方法。 - 請求項7に記載の半導体装置の製造方法において、
前記第1導体膜は、ポリシリコン膜であり、
前記第2導体膜も、ポリシリコン膜である、半導体装置の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018210611A JP7117223B2 (ja) | 2018-11-08 | 2018-11-08 | 半導体装置の製造方法 |
US16/585,802 US11205655B2 (en) | 2018-11-08 | 2019-09-27 | Method for manufacturing semiconductor device including fin-structured transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018210611A JP7117223B2 (ja) | 2018-11-08 | 2018-11-08 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2020077778A JP2020077778A (ja) | 2020-05-21 |
JP7117223B2 true JP7117223B2 (ja) | 2022-08-12 |
Family
ID=70550359
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2018210611A Active JP7117223B2 (ja) | 2018-11-08 | 2018-11-08 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US11205655B2 (ja) |
JP (1) | JP7117223B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11158648B2 (en) * | 2019-03-14 | 2021-10-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Double channel memory device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005203475A (ja) | 2004-01-14 | 2005-07-28 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2006024705A (ja) | 2004-07-07 | 2006-01-26 | Renesas Technology Corp | 不揮発性半導体記憶装置の製造方法、及び不揮発性半導体記憶装置 |
JP2018056453A (ja) | 2016-09-30 | 2018-04-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7812375B2 (en) * | 2003-05-28 | 2010-10-12 | Samsung Electronics Co., Ltd. | Non-volatile memory device and method of fabricating the same |
JP2006041354A (ja) | 2004-07-29 | 2006-02-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US7915691B2 (en) * | 2007-10-30 | 2011-03-29 | International Business Machines Corporation | High density SRAM cell with hybrid devices |
US8106459B2 (en) * | 2008-05-06 | 2012-01-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs having dielectric punch-through stoppers |
US8691651B2 (en) * | 2011-08-25 | 2014-04-08 | United Microelectronics Corp. | Method of forming non-planar FET |
US9337318B2 (en) * | 2012-10-26 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with dummy gate on non-recessed shallow trench isolation (STI) |
US10147806B1 (en) * | 2017-05-23 | 2018-12-04 | United Microelectronics Corp. | Method of fabricating floating gates |
TWI783064B (zh) * | 2018-10-18 | 2022-11-11 | 聯華電子股份有限公司 | 半導體裝置及其形成方法 |
-
2018
- 2018-11-08 JP JP2018210611A patent/JP7117223B2/ja active Active
-
2019
- 2019-09-27 US US16/585,802 patent/US11205655B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005203475A (ja) | 2004-01-14 | 2005-07-28 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2006024705A (ja) | 2004-07-07 | 2006-01-26 | Renesas Technology Corp | 不揮発性半導体記憶装置の製造方法、及び不揮発性半導体記憶装置 |
JP2018056453A (ja) | 2016-09-30 | 2018-04-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US11205655B2 (en) | 2021-12-21 |
US20200152652A1 (en) | 2020-05-14 |
JP2020077778A (ja) | 2020-05-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5538838B2 (ja) | 半導体装置およびその製造方法 | |
US10043814B2 (en) | Semiconductor substrate with a single protruding portion with multiple different widths and insulation thickness | |
US10062706B2 (en) | Semiconductor device | |
JP4758625B2 (ja) | 半導体装置 | |
CN106952920B (zh) | 半导体器件及其制造方法 | |
JP4818061B2 (ja) | 不揮発性半導体メモリ | |
JP2018056378A (ja) | 半導体装置およびその製造方法 | |
US10559581B2 (en) | Semiconductor device | |
JP2006216957A (ja) | 垂直なゲート電極のトランジスタを備える半導体装置及びその製造方法 | |
US11302791B2 (en) | Semiconductor device including a fin-type transistor and method of manufacturing the same | |
JP6998267B2 (ja) | 半導体装置およびその製造方法 | |
JP7232081B2 (ja) | 半導体装置およびその製造方法 | |
JP2019050255A (ja) | 半導体装置およびその製造方法 | |
JP6786440B2 (ja) | 半導体装置およびその製造方法 | |
JP2020004855A (ja) | 半導体装置およびその製造方法 | |
JP7117223B2 (ja) | 半導体装置の製造方法 | |
JP6787798B2 (ja) | 半導体装置の製造方法 | |
JP4758951B2 (ja) | 半導体装置 | |
JP2008034820A (ja) | 不揮発性メモリ素子及びその製造方法 | |
JP2011159712A (ja) | 不揮発性半導体記憶装置、および不揮発性半導体記憶装置の製造方法 | |
JP2012094790A (ja) | 半導体装置およびその製造方法 | |
JP2011171755A (ja) | 半導体装置 | |
JP2010258250A (ja) | 不揮発性半導体記憶装置及びその製造方法 | |
JP2016157728A (ja) | 半導体装置の製造方法 | |
JP2006040985A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20210302 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20211223 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20220104 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20220302 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20220712 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20220801 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7117223 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |