JP5883119B2 - エッジコネクタを有する積層チップ・オン・ボードモジュール - Google Patents
エッジコネクタを有する積層チップ・オン・ボードモジュール Download PDFInfo
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- JP5883119B2 JP5883119B2 JP2014506417A JP2014506417A JP5883119B2 JP 5883119 B2 JP5883119 B2 JP 5883119B2 JP 2014506417 A JP2014506417 A JP 2014506417A JP 2014506417 A JP2014506417 A JP 2014506417A JP 5883119 B2 JP5883119 B2 JP 5883119B2
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Description
本願は、2011年4月21日に出願された米国仮特許出願第61/477,820号および2011年11月29日に出願された米国特許出願第13/306,203号の出願日の利得を主張するものであり、これらの開示内容は、参照することによって、ここに含まれるものとする。以下の本願の譲渡人に譲渡された出願:いずれも2011年4月21日に出願された米国仮特許出願第61/477,877号、第61/477,883号、および第61/477,967号も、参照することによって、ここに含まれるものとする。
本発明は、積層超小型電子アセンブリ、このようなアセンブリを製造する方法、およびこのようなアセンブリに有用な構成要素に関する。
Claims (12)
- モジュールにおいて、
対向する第1および第2の表面であって、各々が第1の方向および前記第1の方向に対して横断する第2の方向に延在している第1および第2の表面と、ソケットの対応する接点と嵌合するように構成されている前記第1および第2の表面の少なくとも1つのエッジに隣接する複数の互いに平行の露出したエッジ接点とを有するモジュールカードであって、前記モジュールカードは、各々が前記第1および第2の表面間に延在している第1および第2の開口を有する、モジュールカードと、
第1および第2の超小型電子素子であって、各超小型電子素子は、前記モジュールカードの前記第1の表面と向き合う前面と、前記前面と対向する裏面とを有し、前記第1の超小型電子素子は、前記第1の超小型電子素子の前記前面および前記裏面間に延在し且つ前記第2の方向に延在する横縁を有し、前記第2の超小型電子素子は、前記モジュールカードの前記第1の表面と向き合う前面を有し、前記第2の超小型電子素子の前記前面は、前記第1の超小型電子素子の前記裏面に向き合い且つ部分的に重なって、該裏面に取り付けられており、前記第2の超小型電子素子の前記前面は、前記第1の超小型電子素子の前記横縁を超えて前記第1の方向に突出しており、前記第1の超小型電子素子のチップ接点は、前記第1の超小型電子素子の前記前面に露出しており且つ前記第1の超小型電子素子の前記前面の中心に隣接して1列または互いに平行の2列に配置されており、前記第2の超小型電子素子のチップ接点は、前記第2の超小型電子素子の前記前面に露出しており且つ前記第2の超小型電子素子の前記前面の中心に隣接して1列または互いに平行の2列に配置されており且つ前記第1の超小型電子素子の前記横縁を超えて配置されており、前記第1の超小型電子素子の前記チップ接点の前記列は、前記第2の超小型電子素子の前記チップ接点の前記列に実質的に直交している、第1および第2の超小型電子素子と、
前記第1の開口内を通って延在し且つ前記第1の超小型電子素子の前記チップ接点に連結している第1のワイヤボンドおよび前記第2の開口内を通って延在し且つ前記第2の超小型電子素子の前記チップ接点に連結している第2のワイヤボンドであって、前記エッジ接点が、前記第1および第2のワイヤボンドを介して前記第1および第2の超小型電子素子に連結されている、第1および第2のワイヤボンドと
を備えている、モジュール。 - 前記エッジ接点は、前記モジュールカードの前記第1および第2の表面の少なくとも1つに露出していることを特徴とする、請求項1に記載のモジュール。
- 前記第1および第2の超小型電子素子の少なくとも1つは、メモリ記憶素子を含んでいることを特徴とする、請求項1に記載のモジュール。
- 前記第1および前記第2の超小型電子素子の少なくとも1つのチップ接点から前記エッジ接点に延在する複数のリードをさらに備えており、前記リードは、前記第1および第2の超小型電子素子の少なくとも1つにおける前記メモリ記憶素子にアドレスを指定するのに用いられるアドレス信号を送るように構成されていることを特徴とする、請求項3に記載のモジュール。
- 複数の第3の超小型電子素子をさらに備えており、前記第3の超小型電子素子の各々は、前記モジュールカードに電気的に連結されていることを特徴とする、請求項1に記載のモジュール。
- 前記複数の第3の超小型電子素子は、積層形態に配置されており、前記第3の超小型電子素子の各々は、前記第3の超小型電子素子の隣接する1つの前面または裏面と向き合う前面または裏面を有していることを特徴とする、請求項5に記載のモジュール。
- 前記複数の第3の超小型電子素子は、平面形態に配置されており、前記第3の超小型電子素子の各々は、前記第3の超小型電子素子の隣接する1つの周面と向き合う周面を有していることを特徴とする、請求項5に記載のモジュール。
- 前記第2の超小型電子素子は、揮発性RAMを含んでおり、前記第3の超小型電子素子の各々は、不揮発性メモリを含んでおり、前記第1の超小型電子素子は、外部コンポーネントと前記第2および第3の超小型電子素子との間のデータの転送を主に制御するように構成されたプロセッサを含んでいることを特徴とする、請求項5に記載のモジュール。
- 前記第2の超小型電子素子は、揮発性フレームバッファメモリ記憶素子を含んでおり、
前記第3の超小型電子素子の各々は、不揮発性メモリを含んでおり、前記第1の超小型電子素子は、グラフィックプロセッサを含んでいることを特徴とする、請求項5に記載のモジュール。 - 前記第1および第2の超小型電子素子の各々は、半導体チップであることを特徴とする、請求項1に記載のモジュール。
- モジュールにおいて、
対向する第1および第2の表面であって、各々が第1の方向および前記第1の方向に対して横断する第2の方向に延在している第1および第2の表面と、ソケットの対応する接点と嵌合するように構成されている前記第1および第2の表面の少なくとも1つのエッジに隣接する複数の互いに平行の露出したエッジ接点とを有するモジュールカードと、
前記モジュールカードの前記第1の表面と向き合う前面を有する第1および第2の超小型電子素子であって、前記超小型電子素子の各々は、前記モジュールカードに電気的に連結されており、前記第1の超小型電子素子の前記前面は前記モジュールカードの前記第1の表面に向き合い、前記第1の超小型電子素子のチップ接点は、前記第1の超小型電子素子の前記前面に露出しており且つ前記第1の超小型電子素子の前記前面の中心に隣接して1列または互いに平行の2列に配置されており、前記第2の超小型電子素子の前記前面は、前記第1の超小型電子素子の裏面に部分的に重なって、該裏面に取り付けられており、前記第2の超小型電子素子の前記前面は、前記第1の超小型電子素子の横縁を超えて第1の方向に突出しており、前記第2の超小型電子素子のチップ接点は、前記第2の超小型電子素子の前記前面に露出しており且つ前記第2の超小型電子素子の前記前面の中心に隣接して1列または互いに平行の2列に配置されており且つ前記第1の超小型電子素子の前記横縁を超えて配置されており、前記第1の超小型電子素子の前記チップ接点の前記列は、前記第2の超小型電子素子の前記チップ接点の前記列に実質的に直交している、第1および第2の超小型電子素子と、
を備えており、
前記第1の超小型電子素子の前記チップ接点および前記エッジ接点に電気的に連結している複数の第1のリードと、前記第2の超小型電子素子の前記チップ接点および前記エッジ接点に電気的に連結している複数の第2のリードとをさらに備えており、
前記モジュールカードは、前記第1および第2の表面間に延在している第1および第2の開口をさらに備えており、前記第1の開口は、前記第1の超小型電子素子の前記チップ接点と真っ直ぐに並んでおり、前記第2の開口は、前記第2の超小型電子素子の前記チップ接点と真っ直ぐに並んでおり、
前記第1のリードは、前記モジュールカードの導電要素から前記第1の超小型電子素子の前記チップ接点に延在する第1のリードボンドを備え、前記第2のリードは、前記導電要素から前記第2の超小型電子素子の前記チップ接点に延在する第2のリードボンドを備えていることを特徴とする、モジュール。 - 前記第1の超小型電子素子の前記チップ接点は、前記第2の開口とは真っ直ぐに並んでおらず、前記第2の超小型電子素子の前記チップ接点は、前記第1の開口とは真っ直ぐに並んでいないことを特徴とする、請求項11に記載のモジュール。
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US201161477820P | 2011-04-21 | 2011-04-21 | |
US61/477,820 | 2011-04-21 | ||
US13/306,203 | 2011-11-29 | ||
US13/306,203 US8633576B2 (en) | 2011-04-21 | 2011-11-29 | Stacked chip-on-board module with edge connector |
PCT/US2012/029876 WO2012145115A1 (en) | 2011-04-21 | 2012-03-21 | Stacked chip-on-board module with edge connector |
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JP2014512686A5 JP2014512686A5 (ja) | 2015-05-07 |
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Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8659143B2 (en) | 2011-10-03 | 2014-02-25 | Invensas Corporation | Stub minimization for wirebond assemblies without windows |
US8653646B2 (en) | 2011-10-03 | 2014-02-18 | Invensas Corporation | Stub minimization using duplicate sets of terminals for wirebond assemblies without windows |
KR20130118175A (ko) * | 2012-04-19 | 2013-10-29 | 삼성전자주식회사 | 반도체 패키지 및 그의 제조 방법 |
US8907500B2 (en) | 2013-02-04 | 2014-12-09 | Invensas Corporation | Multi-die wirebond packages with elongated windows |
US9490195B1 (en) | 2015-07-17 | 2016-11-08 | Invensas Corporation | Wafer-level flipped die stacks with leadframes or metal foil interconnects |
US9825002B2 (en) | 2015-07-17 | 2017-11-21 | Invensas Corporation | Flipped die stack |
US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
US9484080B1 (en) | 2015-11-09 | 2016-11-01 | Invensas Corporation | High-bandwidth memory application with controlled impedance loading |
US9508691B1 (en) | 2015-12-16 | 2016-11-29 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
US20170186474A1 (en) * | 2015-12-28 | 2017-06-29 | Invensas Corporation | Dual-channel dimm |
WO2017135967A1 (en) * | 2016-02-05 | 2017-08-10 | Hewlett Packard Enterprise Development Lp | Dual in-line memory module |
US10629351B2 (en) | 2016-02-16 | 2020-04-21 | Sony Corporation | Semiconductor device, semiconductor chip, and system |
US10566310B2 (en) | 2016-04-11 | 2020-02-18 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
US9595511B1 (en) | 2016-05-12 | 2017-03-14 | Invensas Corporation | Microelectronic packages and assemblies with improved flyby signaling operation |
US9728524B1 (en) | 2016-06-30 | 2017-08-08 | Invensas Corporation | Enhanced density assembly having microelectronic packages mounted at substantial angle to board |
KR102358842B1 (ko) * | 2017-08-21 | 2022-02-07 | 쑤저우 레킨 세미컨덕터 컴퍼니 리미티드 | 발광소자 패키지 및 광원 장치 |
TWI657237B (zh) * | 2018-02-21 | 2019-04-21 | 茂達電子股份有限公司 | 光學偵測裝置及光學封裝結構 |
EP4158679A4 (en) | 2020-05-29 | 2024-07-10 | Formfactor Inc | 3D ELECTRICAL INTEGRATION WITH COMPONENT CARRIER EDGE CONNECTIONS TO A 2D CONTACT ARRANGEMENT |
Family Cites Families (226)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62107391A (ja) | 1985-11-06 | 1987-05-18 | Nippon Texas Instr Kk | 情報記憶媒体 |
US5138438A (en) | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
JPH02174255A (ja) | 1988-12-27 | 1990-07-05 | Mitsubishi Electric Corp | 半導体集積回路装置 |
US5679977A (en) | 1990-09-24 | 1997-10-21 | Tessera, Inc. | Semiconductor chip assemblies, methods of making same and components for same |
US5148266A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies having interposer and flexible lead |
US5148265A (en) | 1990-09-24 | 1992-09-15 | Ist Associates, Inc. | Semiconductor chip assemblies with fan-in leads |
US5222014A (en) | 1992-03-02 | 1993-06-22 | Motorola, Inc. | Three-dimensional multi-chip pad array carrier |
US5369552A (en) | 1992-07-14 | 1994-11-29 | Ncr Corporation | Multi-chip module with multiple compartments |
US5915752A (en) | 1992-07-24 | 1999-06-29 | Tessera, Inc. | Method of making connections to a semiconductor chip assembly |
JP3487524B2 (ja) | 1994-12-20 | 2004-01-19 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US5998864A (en) | 1995-05-26 | 1999-12-07 | Formfactor, Inc. | Stacking semiconductor devices, particularly memory chips |
US5861666A (en) | 1995-08-30 | 1999-01-19 | Tessera, Inc. | Stacked chip assembly |
KR100204753B1 (ko) | 1996-03-08 | 1999-06-15 | 윤종용 | 엘오씨 유형의 적층 칩 패키지 |
JP2806357B2 (ja) | 1996-04-18 | 1998-09-30 | 日本電気株式会社 | スタックモジュール |
US5892660A (en) * | 1996-08-29 | 1999-04-06 | Micron Technology, Inc. | Single in line memory module adapter |
WO1998012568A1 (en) * | 1996-09-18 | 1998-03-26 | Hitachi, Ltd. | Process for producing semiconductor device and semiconductor device |
US6335565B1 (en) | 1996-12-04 | 2002-01-01 | Hitachi, Ltd. | Semiconductor device |
JP2978861B2 (ja) | 1997-10-28 | 1999-11-15 | 九州日本電気株式会社 | モールドbga型半導体装置及びその製造方法 |
JP3393800B2 (ja) | 1997-11-05 | 2003-04-07 | 新光電気工業株式会社 | 半導体装置の製造方法 |
JP3718039B2 (ja) * | 1997-12-17 | 2005-11-16 | 株式会社日立製作所 | 半導体装置およびそれを用いた電子装置 |
US6343019B1 (en) * | 1997-12-22 | 2002-01-29 | Micron Technology, Inc. | Apparatus and method of stacking die on a substrate |
US6742098B1 (en) | 2000-10-03 | 2004-05-25 | Intel Corporation | Dual-port buffer-to-memory interface |
US6021048A (en) | 1998-02-17 | 2000-02-01 | Smith; Gary W. | High speed memory module |
US6150724A (en) | 1998-03-02 | 2000-11-21 | Motorola, Inc. | Multi-chip semiconductor device and method for making the device by using multiple flip chip interfaces |
US6072233A (en) | 1998-05-04 | 2000-06-06 | Micron Technology, Inc. | Stackable ball grid array package |
US6180881B1 (en) | 1998-05-05 | 2001-01-30 | Harlan Ruben Isaak | Chip stack and method of making same |
US6369444B1 (en) * | 1998-05-19 | 2002-04-09 | Agere Systems Guardian Corp. | Packaging silicon on silicon multichip modules |
US5977640A (en) | 1998-06-26 | 1999-11-02 | International Business Machines Corporation | Highly integrated chip-on-chip packaging |
US7525813B2 (en) | 1998-07-06 | 2009-04-28 | Renesas Technology Corp. | Semiconductor device |
US6353539B1 (en) | 1998-07-21 | 2002-03-05 | Intel Corporation | Method and apparatus for matched length routing of back-to-back package placement |
JP3484985B2 (ja) | 1998-08-17 | 2004-01-06 | 東亞合成株式会社 | 光硬化型接着剤組成物 |
US6121576A (en) | 1998-09-02 | 2000-09-19 | Micron Technology, Inc. | Method and process of contact to a heat softened solder ball array |
US6093029A (en) | 1998-09-08 | 2000-07-25 | S3 Incorporated | Vertically stackable integrated circuit |
US6201695B1 (en) * | 1998-10-26 | 2001-03-13 | Micron Technology, Inc. | Heat sink for chip stacking applications |
US6815251B1 (en) * | 1999-02-01 | 2004-11-09 | Micron Technology, Inc. | High density modularity for IC's |
JP2000243875A (ja) | 1999-02-23 | 2000-09-08 | Shinko Electric Ind Co Ltd | 半導体装置 |
SE519108C2 (sv) | 1999-05-06 | 2003-01-14 | Sandvik Ab | Belagt skärverktyg för bearbetning av grått gjutjärn |
TW409377B (en) | 1999-05-21 | 2000-10-21 | Siliconware Precision Industries Co Ltd | Small scale ball grid array package |
KR100393095B1 (ko) | 1999-06-12 | 2003-07-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지와 그 제조방법 |
JP3360655B2 (ja) | 1999-07-08 | 2002-12-24 | 日本電気株式会社 | 半導体装置 |
JP2001053243A (ja) * | 1999-08-06 | 2001-02-23 | Hitachi Ltd | 半導体記憶装置とメモリモジュール |
JP4526651B2 (ja) | 1999-08-12 | 2010-08-18 | 富士通セミコンダクター株式会社 | 半導体装置 |
US6199743B1 (en) | 1999-08-19 | 2001-03-13 | Micron Technology, Inc. | Apparatuses for forming wire bonds from circuitry on a substrate to a semiconductor chip, and methods of forming semiconductor chip assemblies |
JP2001085609A (ja) | 1999-09-17 | 2001-03-30 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2001196407A (ja) | 2000-01-14 | 2001-07-19 | Seiko Instruments Inc | 半導体装置および半導体装置の形成方法 |
US6369448B1 (en) | 2000-01-21 | 2002-04-09 | Lsi Logic Corporation | Vertically integrated flip chip semiconductor package |
US6414396B1 (en) | 2000-01-24 | 2002-07-02 | Amkor Technology, Inc. | Package for stacked integrated circuits |
JP3768761B2 (ja) | 2000-01-31 | 2006-04-19 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
JP2001223324A (ja) | 2000-02-10 | 2001-08-17 | Mitsubishi Electric Corp | 半導体装置 |
TW579555B (en) | 2000-03-13 | 2004-03-11 | Ibm | Semiconductor chip package and packaging of integrated circuit chip in electronic apparatus |
US6731009B1 (en) | 2000-03-20 | 2004-05-04 | Cypress Semiconductor Corporation | Multi-die assembly |
KR100583491B1 (ko) | 2000-04-07 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 및 그 제조방법 |
JP2002043875A (ja) | 2000-07-24 | 2002-02-08 | Nec Corp | 可変利得増幅器及びそれを備えた電子機器 |
JP2002076252A (ja) | 2000-08-31 | 2002-03-15 | Nec Kyushu Ltd | 半導体装置 |
JP3874062B2 (ja) | 2000-09-05 | 2007-01-31 | セイコーエプソン株式会社 | 半導体装置 |
JP3462166B2 (ja) | 2000-09-08 | 2003-11-05 | 富士通カンタムデバイス株式会社 | 化合物半導体装置 |
US6492726B1 (en) | 2000-09-22 | 2002-12-10 | Chartered Semiconductor Manufacturing Ltd. | Chip scale packaging with multi-layer flip chip arrangement and ball grid array interconnection |
TW511405B (en) | 2000-12-27 | 2002-11-21 | Matsushita Electric Ind Co Ltd | Device built-in module and manufacturing method thereof |
SG95637A1 (en) | 2001-03-15 | 2003-04-23 | Micron Technology Inc | Semiconductor/printed circuit board assembly, and computer system |
SG106054A1 (en) | 2001-04-17 | 2004-09-30 | Micron Technology Inc | Method and apparatus for package reduction in stacked chip and board assemblies |
JP2002353398A (ja) | 2001-05-25 | 2002-12-06 | Nec Kyushu Ltd | 半導体装置 |
US6472741B1 (en) | 2001-07-14 | 2002-10-29 | Siliconware Precision Industries Co., Ltd. | Thermally-enhanced stacked-die ball grid array semiconductor package and method of fabricating the same |
US6385049B1 (en) | 2001-07-05 | 2002-05-07 | Walsin Advanced Electronics Ltd | Multi-board BGA package |
US6765287B1 (en) | 2001-07-27 | 2004-07-20 | Charles W. C. Lin | Three-dimensional stacked semiconductor package |
US7176506B2 (en) | 2001-08-28 | 2007-02-13 | Tessera, Inc. | High frequency chip packages with connecting elements |
JP2003101207A (ja) | 2001-09-27 | 2003-04-04 | Nec Kyushu Ltd | 半田ボールおよびそれを用いた部品接続構造 |
US6977440B2 (en) | 2001-10-09 | 2005-12-20 | Tessera, Inc. | Stacked packages |
SG118103A1 (en) | 2001-12-12 | 2006-01-27 | Micron Technology Inc | BOC BGA package for die with I-shaped bond pad layout |
KR100480909B1 (ko) | 2001-12-29 | 2005-04-07 | 주식회사 하이닉스반도체 | 적층 칩 패키지의 제조 방법 |
TW523890B (en) * | 2002-02-07 | 2003-03-11 | Macronix Int Co Ltd | Stacked semiconductor packaging device |
SG121705A1 (en) | 2002-02-21 | 2006-05-26 | United Test & Assembly Ct Ltd | Semiconductor package |
US7196415B2 (en) | 2002-03-22 | 2007-03-27 | Broadcom Corporation | Low voltage drop and high thermal performance ball grid array package |
DE10215654A1 (de) | 2002-04-09 | 2003-11-06 | Infineon Technologies Ag | Elektronisches Bauteil mit mindestens einem Halbleiterchip und Flip-Chip-Kontakten sowie Verfahren zu seiner Herstellung |
US6924496B2 (en) * | 2002-05-31 | 2005-08-02 | Fujitsu Limited | Fingerprint sensor and interconnect |
US7482699B2 (en) | 2002-06-05 | 2009-01-27 | Renesas Technology Corp. | Semiconductor device |
US7132311B2 (en) | 2002-07-26 | 2006-11-07 | Intel Corporation | Encapsulation of a stack of semiconductor dice |
JP2004063767A (ja) | 2002-07-29 | 2004-02-26 | Renesas Technology Corp | 半導体装置 |
US6762942B1 (en) * | 2002-09-05 | 2004-07-13 | Gary W. Smith | Break away, high speed, folded, jumperless electronic assembly |
TW557556B (en) | 2002-09-10 | 2003-10-11 | Siliconware Precision Industries Co Ltd | Window-type multi-chip semiconductor package |
JP3866178B2 (ja) | 2002-10-08 | 2007-01-10 | 株式会社ルネサステクノロジ | Icカード |
AU2003301632A1 (en) * | 2002-10-22 | 2004-05-13 | Unitive International Limited | Stacked electronic structures including offset substrates |
JP4110992B2 (ja) | 2003-02-07 | 2008-07-02 | セイコーエプソン株式会社 | 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法 |
JP4504204B2 (ja) | 2003-02-25 | 2010-07-14 | テッセラ,インコーポレイテッド | 接続要素を有する高周波チップパッケージ |
US7268425B2 (en) | 2003-03-05 | 2007-09-11 | Intel Corporation | Thermally enhanced electronic flip-chip packaging with external-connector-side die and method |
TW200419752A (en) | 2003-03-18 | 2004-10-01 | United Test Ct Inc | Semiconductor package with heat sink |
TWI313049B (en) * | 2003-04-23 | 2009-08-01 | Advanced Semiconductor Eng | Multi-chips stacked package |
US7528421B2 (en) | 2003-05-05 | 2009-05-05 | Lamina Lighting, Inc. | Surface mountable light emitting diode assemblies packaged for high temperature operation |
KR20050001159A (ko) | 2003-06-27 | 2005-01-06 | 삼성전자주식회사 | 복수개의 플립 칩들을 갖는 멀티칩 패키지 및 그 제조방법 |
KR100493063B1 (ko) | 2003-07-18 | 2005-06-02 | 삼성전자주식회사 | 스택 반도체 칩 비지에이 패키지 및 그 제조방법 |
SG148877A1 (en) | 2003-07-22 | 2009-01-29 | Micron Technology Inc | Semiconductor substrates including input/output redistribution using wire bonds and anisotropically conductive film, methods of fabrication and assemblies including same |
US7462936B2 (en) | 2003-10-06 | 2008-12-09 | Tessera, Inc. | Formation of circuitry with modification of feature height |
US7061121B2 (en) | 2003-11-12 | 2006-06-13 | Tessera, Inc. | Stacked microelectronic assemblies with central contacts |
US7095104B2 (en) * | 2003-11-21 | 2006-08-22 | International Business Machines Corporation | Overlap stacking of center bus bonded memory chips for double density and method of manufacturing the same |
US7440286B2 (en) | 2005-04-21 | 2008-10-21 | Super Talent Electronics, Inc. | Extended USB dual-personality card reader |
JP2005166892A (ja) * | 2003-12-02 | 2005-06-23 | Kingpak Technology Inc | スタック型小型メモリカード |
US8998620B2 (en) | 2003-12-02 | 2015-04-07 | Super Talent Technology, Corp. | Molding method for COB-EUSB devices and metal housing package |
DE10360708B4 (de) | 2003-12-19 | 2008-04-10 | Infineon Technologies Ag | Halbleitermodul mit einem Halbleiterstapel, Umverdrahtungsplatte, und Verfahren zur Herstellung derselben |
US20050173807A1 (en) * | 2004-02-05 | 2005-08-11 | Jianbai Zhu | High density vertically stacked semiconductor device |
JP4370513B2 (ja) | 2004-02-27 | 2009-11-25 | エルピーダメモリ株式会社 | 半導体装置 |
JP2005251957A (ja) | 2004-03-04 | 2005-09-15 | Renesas Technology Corp | 半導体装置 |
US7489517B2 (en) | 2004-04-05 | 2009-02-10 | Thomas Joel Massingill | Die down semiconductor package |
US7078808B2 (en) | 2004-05-20 | 2006-07-18 | Texas Instruments Incorporated | Double density method for wirebond interconnect |
JP4844391B2 (ja) | 2004-05-21 | 2011-12-28 | 日本電気株式会社 | 半導体装置並びに配線基板及びその製造方法 |
KR20050119414A (ko) | 2004-06-16 | 2005-12-21 | 삼성전자주식회사 | 에지 패드형 반도체 칩의 스택 패키지 및 그 제조방법 |
KR20060004298A (ko) | 2004-07-09 | 2006-01-12 | 삼성테크윈 주식회사 | 무선 전자 라벨 |
US7381593B2 (en) * | 2004-08-05 | 2008-06-03 | St Assembly Test Services Ltd. | Method and apparatus for stacked die packaging |
JP4445351B2 (ja) | 2004-08-31 | 2010-04-07 | 株式会社東芝 | 半導体モジュール |
US20060049513A1 (en) | 2004-09-03 | 2006-03-09 | Staktek Group L.P. | Thin module system and method with thermal management |
JP4601365B2 (ja) | 2004-09-21 | 2010-12-22 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US20060097400A1 (en) | 2004-11-03 | 2006-05-11 | Texas Instruments Incorporated | Substrate via pad structure providing reliable connectivity in array package devices |
US7786567B2 (en) | 2004-11-10 | 2010-08-31 | Chung-Cheng Wang | Substrate for electrical device and methods for making the same |
US7217994B2 (en) * | 2004-12-01 | 2007-05-15 | Kyocera Wireless Corp. | Stack package for high density integrated circuits |
TWI256092B (en) | 2004-12-02 | 2006-06-01 | Siliconware Precision Industries Co Ltd | Semiconductor package and fabrication method thereof |
JP2006172122A (ja) | 2004-12-15 | 2006-06-29 | Toshiba Corp | カード状記憶装置 |
CN100435324C (zh) | 2004-12-20 | 2008-11-19 | 半导体元件工业有限责任公司 | 具有增强散热性的半导体封装结构 |
JP4086068B2 (ja) | 2004-12-27 | 2008-05-14 | 日本電気株式会社 | 半導体装置 |
KR20060080424A (ko) | 2005-01-05 | 2006-07-10 | 삼성전자주식회사 | 멀티 칩 패키지를 장착하는 메모리 카드 |
US7112875B1 (en) | 2005-02-17 | 2006-09-26 | Amkor Technology, Inc. | Secure digital memory card using land grid array structure |
US7205656B2 (en) | 2005-02-22 | 2007-04-17 | Micron Technology, Inc. | Stacked device package for peripheral and center device pad layout device |
KR100630741B1 (ko) | 2005-03-04 | 2006-10-02 | 삼성전자주식회사 | 다중 몰딩에 의한 적층형 반도체 패키지 및 그 제조방법 |
US7196427B2 (en) | 2005-04-18 | 2007-03-27 | Freescale Semiconductor, Inc. | Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element |
JP4704800B2 (ja) | 2005-04-19 | 2011-06-22 | エルピーダメモリ株式会社 | 積層型半導体装置及びその製造方法 |
US7250675B2 (en) * | 2005-05-05 | 2007-07-31 | International Business Machines Corporation | Method and apparatus for forming stacked die and substrate structures for increased packing density |
KR101070913B1 (ko) | 2005-05-19 | 2011-10-06 | 삼성테크윈 주식회사 | 반도체 칩 적층 패키지 |
US7402911B2 (en) | 2005-06-28 | 2008-07-22 | Infineon Technologies Ag | Multi-chip device and method for producing a multi-chip device |
SG130066A1 (en) | 2005-08-26 | 2007-03-20 | Micron Technology Inc | Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices |
DE102005041451A1 (de) * | 2005-08-31 | 2007-03-01 | Infineon Technologies Ag | Elektronische Steckeinheit |
JP4108701B2 (ja) | 2005-09-12 | 2008-06-25 | 株式会社ルネサステクノロジ | Icカードの製造方法 |
US7602054B2 (en) | 2005-10-05 | 2009-10-13 | Semiconductor Components Industries, L.L.C. | Method of forming a molded array package device having an exposed tab and structure |
JP2007123595A (ja) | 2005-10-28 | 2007-05-17 | Nec Corp | 半導体装置及びその実装構造 |
JP2007134426A (ja) | 2005-11-09 | 2007-05-31 | Renesas Technology Corp | マルチチップモジュール |
US20070152310A1 (en) | 2005-12-29 | 2007-07-05 | Tessera, Inc. | Electrical ground method for ball stack package |
KR100673965B1 (ko) | 2006-01-11 | 2007-01-24 | 삼성테크윈 주식회사 | 인쇄회로기판 및 반도체 패키지 제조방법 |
JP2007188916A (ja) | 2006-01-11 | 2007-07-26 | Renesas Technology Corp | 半導体装置 |
KR100690247B1 (ko) | 2006-01-16 | 2007-03-12 | 삼성전자주식회사 | 이중 봉합된 반도체 패키지 및 그의 제조 방법 |
US20070176297A1 (en) | 2006-01-31 | 2007-08-02 | Tessera, Inc. | Reworkable stacked chip assembly |
CN101375299B (zh) | 2006-02-02 | 2012-08-08 | 松下电器产业株式会社 | 存储卡及存储卡的制造方法 |
SG135074A1 (en) | 2006-02-28 | 2007-09-28 | Micron Technology Inc | Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices |
KR20070088177A (ko) | 2006-02-24 | 2007-08-29 | 삼성테크윈 주식회사 | 반도체 패키지 및 그 제조 방법 |
US20080029879A1 (en) | 2006-03-01 | 2008-02-07 | Tessera, Inc. | Structure and method of making lidded chips |
US7514780B2 (en) | 2006-03-15 | 2009-04-07 | Hitachi, Ltd. | Power semiconductor device |
US7368319B2 (en) | 2006-03-17 | 2008-05-06 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
US7768075B2 (en) | 2006-04-06 | 2010-08-03 | Fairchild Semiconductor Corporation | Semiconductor die packages using thin dies and metal substrates |
CN100511588C (zh) | 2006-04-14 | 2009-07-08 | 泰特科技股份有限公司 | 导线架型芯片级封装方法 |
US20070241441A1 (en) | 2006-04-17 | 2007-10-18 | Stats Chippac Ltd. | Multichip package system |
SG136822A1 (en) | 2006-04-19 | 2007-11-29 | Micron Technology Inc | Integrated circuit devices with stacked package interposers |
TW200743190A (en) | 2006-05-10 | 2007-11-16 | Chung-Cheng Wang | A heat spreader for electrical device |
JP5026736B2 (ja) | 2006-05-15 | 2012-09-19 | パナソニックヘルスケア株式会社 | 冷凍装置 |
JP5069745B2 (ja) | 2006-06-20 | 2012-11-07 | エヌエックスピー ビー ヴィ | 集積回路及びこれを備えるアセンブリ |
US20080023805A1 (en) | 2006-07-26 | 2008-01-31 | Texas Instruments Incorporated | Array-Processed Stacked Semiconductor Packages |
TWI306658B (en) | 2006-08-07 | 2009-02-21 | Chipmos Technologies Inc | Leadframe on offset stacked chips package |
US7638868B2 (en) | 2006-08-16 | 2009-12-29 | Tessera, Inc. | Microelectronic package |
US7906844B2 (en) | 2006-09-26 | 2011-03-15 | Compass Technology Co. Ltd. | Multiple integrated circuit die package with thermal performance |
TWI370515B (en) | 2006-09-29 | 2012-08-11 | Megica Corp | Circuit component |
KR100825784B1 (ko) | 2006-10-18 | 2008-04-28 | 삼성전자주식회사 | 휨 및 와이어 단선을 억제하는 반도체 패키지 및 그제조방법 |
KR100885911B1 (ko) | 2006-11-16 | 2009-02-26 | 삼성전자주식회사 | 열방출 특성을 개선한 반도체 패키지 |
JP4389228B2 (ja) | 2006-11-29 | 2009-12-24 | エルピーダメモリ株式会社 | メモリモジュール |
US7772683B2 (en) | 2006-12-09 | 2010-08-10 | Stats Chippac Ltd. | Stacked integrated circuit package-in-package system |
KR101533120B1 (ko) | 2006-12-14 | 2015-07-01 | 램버스 인코포레이티드 | 멀티 다이 메모리 디바이스 |
JP2008177241A (ja) | 2007-01-16 | 2008-07-31 | Toshiba Corp | 半導体パッケージ |
CN101232004A (zh) | 2007-01-23 | 2008-07-30 | 联华电子股份有限公司 | 芯片堆叠封装结构 |
CN101617400A (zh) | 2007-01-31 | 2009-12-30 | 富士通微电子株式会社 | 半导体器件及其制造方法 |
JP5285224B2 (ja) | 2007-01-31 | 2013-09-11 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 回路装置 |
JP2008198841A (ja) | 2007-02-14 | 2008-08-28 | Elpida Memory Inc | 半導体装置 |
JP2008235576A (ja) | 2007-03-20 | 2008-10-02 | Fujitsu Ltd | 電子部品の放熱構造及び半導体装置 |
US20080237844A1 (en) | 2007-03-28 | 2008-10-02 | Aleksandar Aleksov | Microelectronic package and method of manufacturing same |
US7638869B2 (en) | 2007-03-28 | 2009-12-29 | Qimonda Ag | Semiconductor device |
US20080237887A1 (en) | 2007-03-29 | 2008-10-02 | Hem Takiar | Semiconductor die stack having heightened contact for wire bond |
US7872356B2 (en) * | 2007-05-16 | 2011-01-18 | Qualcomm Incorporated | Die stacking system and method |
US20080296717A1 (en) | 2007-06-01 | 2008-12-04 | Tessera, Inc. | Packages and assemblies including lidded chips |
JP2008306128A (ja) | 2007-06-11 | 2008-12-18 | Shinko Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US8384199B2 (en) | 2007-06-25 | 2013-02-26 | Epic Technologies, Inc. | Integrated conductive structures and fabrication methods thereof facilitating implementing a cell phone or other electronic system |
KR100876889B1 (ko) | 2007-06-26 | 2009-01-07 | 주식회사 하이닉스반도체 | 반도체 패키지 및 이를 이용한 멀티칩 반도체 패키지 |
SG148901A1 (en) | 2007-07-09 | 2009-01-29 | Micron Technology Inc | Packaged semiconductor assemblies and methods for manufacturing such assemblies |
KR101341566B1 (ko) | 2007-07-10 | 2013-12-16 | 삼성전자주식회사 | 소켓, 검사 장치, 그리고 적층형 반도체 소자 제조 방법 |
US8299626B2 (en) | 2007-08-16 | 2012-10-30 | Tessera, Inc. | Microelectronic package |
US7442045B1 (en) | 2007-08-17 | 2008-10-28 | Centipede Systems, Inc. | Miniature electrical ball and tube socket with self-capturing multiple-contact-point coupling |
US20090051043A1 (en) * | 2007-08-21 | 2009-02-26 | Spansion Llc | Die stacking in multi-die stacks using die support mechanisms |
US7872340B2 (en) * | 2007-08-31 | 2011-01-18 | Stats Chippac Ltd. | Integrated circuit package system employing an offset stacked configuration |
US7880310B2 (en) | 2007-09-28 | 2011-02-01 | Intel Corporation | Direct device attachment on dual-mode wirebond die |
US7851267B2 (en) | 2007-10-18 | 2010-12-14 | Infineon Technologies Ag | Power semiconductor module method |
JP2009164160A (ja) | 2007-12-28 | 2009-07-23 | Panasonic Corp | 半導体デバイス積層体および実装方法 |
US20090166065A1 (en) | 2008-01-02 | 2009-07-02 | Clayton James E | Thin multi-chip flex module |
US8138610B2 (en) * | 2008-02-08 | 2012-03-20 | Qimonda Ag | Multi-chip package with interconnected stacked chips |
JP5207868B2 (ja) | 2008-02-08 | 2013-06-12 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US8354742B2 (en) * | 2008-03-31 | 2013-01-15 | Stats Chippac, Ltd. | Method and apparatus for a package having multiple stacked die |
US8159052B2 (en) | 2008-04-10 | 2012-04-17 | Semtech Corporation | Apparatus and method for a chip assembly including a frequency extending device |
US7928562B2 (en) | 2008-07-22 | 2011-04-19 | International Business Machines Corporation | Segmentation of a die stack for 3D packaging thermal management |
US20100044861A1 (en) | 2008-08-20 | 2010-02-25 | Chin-Tien Chiu | Semiconductor die support in an offset die stack |
US8253231B2 (en) | 2008-09-23 | 2012-08-28 | Marvell International Ltd. | Stacked integrated circuit package using a window substrate |
KR101479461B1 (ko) | 2008-10-14 | 2015-01-06 | 삼성전자주식회사 | 적층 패키지 및 이의 제조 방법 |
JP5056718B2 (ja) | 2008-10-16 | 2012-10-24 | 株式会社デンソー | 電子装置の製造方法 |
JP5176893B2 (ja) | 2008-11-18 | 2013-04-03 | 日立金属株式会社 | はんだボール |
US8049339B2 (en) | 2008-11-24 | 2011-11-01 | Powertech Technology Inc. | Semiconductor package having isolated inner lead |
US7951643B2 (en) | 2008-11-29 | 2011-05-31 | Stats Chippac Ltd. | Integrated circuit packaging system with lead frame and method of manufacture thereof |
KR101011863B1 (ko) | 2008-12-02 | 2011-01-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
US20100193930A1 (en) * | 2009-02-02 | 2010-08-05 | Samsung Electronics Co., Ltd. | Multi-chip semiconductor devices having conductive vias and methods of forming the same |
US8026589B1 (en) | 2009-02-23 | 2011-09-27 | Amkor Technology, Inc. | Reduced profile stackable semiconductor package |
JP5671681B2 (ja) | 2009-03-05 | 2015-02-18 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 積層型半導体装置 |
KR20120068985A (ko) | 2009-03-13 | 2012-06-27 | 테세라, 인코포레이티드 | 본드 패드를 통과하여 연장된 비아를 갖는 마이크로전자 소자를 포함하는 적층형 마이크로전자 어셈블리 |
US8026608B2 (en) | 2009-03-24 | 2011-09-27 | General Electric Company | Stackable electronic package |
KR101566407B1 (ko) | 2009-03-25 | 2015-11-05 | 삼성전자주식회사 | 적층 메모리 소자 |
TWI401785B (zh) | 2009-03-27 | 2013-07-11 | Chipmos Technologies Inc | 多晶片堆疊封裝 |
US8039316B2 (en) | 2009-04-14 | 2011-10-18 | Stats Chippac Ltd. | Integrated circuit packaging system with stacked integrated circuit and heat spreader with openings and method of manufacture thereof |
KR101601847B1 (ko) * | 2009-05-21 | 2016-03-09 | 삼성전자주식회사 | 반도체 패키지 |
KR20100134354A (ko) | 2009-06-15 | 2010-12-23 | 삼성전자주식회사 | 반도체 패키지, 스택 모듈, 카드 및 전자 시스템 |
TWM370767U (en) * | 2009-06-19 | 2009-12-11 | fu-zhi Huang | Modulized computer |
US20100327419A1 (en) * | 2009-06-26 | 2010-12-30 | Sriram Muthukumar | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same |
TWI474331B (zh) | 2009-06-30 | 2015-02-21 | Hitachi Ltd | Semiconductor device |
US20110085304A1 (en) | 2009-10-14 | 2011-04-14 | Irvine Sensors Corporation | Thermal management device comprising thermally conductive heat spreader with electrically isolated through-hole vias |
US20110309152A1 (en) | 2010-06-22 | 2011-12-22 | Kim Young-Sun | Plastic card package and plastic card package manufacturing method |
US10128206B2 (en) | 2010-10-14 | 2018-11-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Conductive pillar structure |
US8553420B2 (en) * | 2010-10-19 | 2013-10-08 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics |
US8378478B2 (en) | 2010-11-24 | 2013-02-19 | Tessera, Inc. | Enhanced stacked microelectronic assemblies with central contacts and vias connected to the central contacts |
KR101061531B1 (ko) | 2010-12-17 | 2011-09-01 | 테세라 리써치 엘엘씨 | 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체 |
KR101118711B1 (ko) | 2010-12-17 | 2012-03-12 | 테세라, 인코포레이티드 | 중앙 콘택을 구비한 적층형 마이크로전자 조립체 |
TW201239998A (en) | 2011-03-16 | 2012-10-01 | Walton Advanced Eng Inc | Method for mold array process to prevent peripheries of substrate exposed |
US8928153B2 (en) * | 2011-04-21 | 2015-01-06 | Tessera, Inc. | Flip-chip, face-up and face-down centerbond memory wirebond assemblies |
US9013033B2 (en) | 2011-04-21 | 2015-04-21 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8338963B2 (en) | 2011-04-21 | 2012-12-25 | Tessera, Inc. | Multiple die face-down stacking for two or more die |
US8304881B1 (en) | 2011-04-21 | 2012-11-06 | Tessera, Inc. | Flip-chip, face-up and face-down wirebond combination package |
US8970028B2 (en) | 2011-12-29 | 2015-03-03 | Invensas Corporation | Embedded heat spreader for package with multiple microelectronic elements and face-down connection |
US8502390B2 (en) * | 2011-07-12 | 2013-08-06 | Tessera, Inc. | De-skewed multi-die packages |
US8436457B2 (en) | 2011-10-03 | 2013-05-07 | Invensas Corporation | Stub minimization for multi-die wirebond assemblies with parallel windows |
US8723327B2 (en) * | 2011-10-20 | 2014-05-13 | Invensas Corporation | Microelectronic package with stacked microelectronic units and method for manufacture thereof |
KR102642330B1 (ko) * | 2016-07-19 | 2024-03-05 | 삼성디스플레이 주식회사 | 유기발광소자 및 이를 포함하는 표시장치 |
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US20160190048A1 (en) | 2016-06-30 |
JP2014512686A (ja) | 2014-05-22 |
TWI493795B (zh) | 2015-07-21 |
BR112013027143A2 (pt) | 2017-01-10 |
US20170263540A1 (en) | 2017-09-14 |
EP2700096A1 (en) | 2014-02-26 |
TW201304287A (zh) | 2013-01-16 |
CN103620775A (zh) | 2014-03-05 |
US8633576B2 (en) | 2014-01-21 |
US9281266B2 (en) | 2016-03-08 |
US20120267771A1 (en) | 2012-10-25 |
US9735093B2 (en) | 2017-08-15 |
US20140131849A1 (en) | 2014-05-15 |
KR20140027999A (ko) | 2014-03-07 |
US10622289B2 (en) | 2020-04-14 |
WO2012145115A1 (en) | 2012-10-26 |
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