TWI488183B - 一封裝中之記憶體模組 - Google Patents

一封裝中之記憶體模組 Download PDF

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Publication number
TWI488183B
TWI488183B TW101125191A TW101125191A TWI488183B TW I488183 B TWI488183 B TW I488183B TW 101125191 A TW101125191 A TW 101125191A TW 101125191 A TW101125191 A TW 101125191A TW I488183 B TWI488183 B TW I488183B
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Taiwan
Prior art keywords
microelectronic
package
components
component
microelectronic package
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TW101125191A
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English (en)
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TW201308329A (zh
Inventor
Belgacem Haba
Wael Zohni
Richard Dewitt Crisp
Ilyas Mohammed
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Invensas Corp
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Publication of TW201308329A publication Critical patent/TW201308329A/zh
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Publication of TWI488183B publication Critical patent/TWI488183B/zh

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    • H—ELECTRICITY
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    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
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Description

一封裝中之記憶體模組
本發明之標的物係關於微電子封裝及併入有微電子封裝之總成。
本申請案係2012年1月9日提出申請之美國專利申請案第13/346,201號之一接續案，其主張皆於2011年10月3日提出申請之美國臨時專利申請案第61/542,488、61/542,495及61/542,553號以及2011年7月12日提出申請之美國臨時專利申請案第61/506,889號之申請日期之權益，該等申請案之揭示內容皆以引用的方式併入本文中。
半導體晶片通常係提供為個別經預封裝單元。一標準晶片具有一扁平矩形主體，其中一大的前面具有連接至該晶片之內部電路之觸點。每一個別晶片通常係含納於一封裝中，該封裝具有連接至該晶片之該等觸點之外部端子。該等端子(亦即，該封裝之外部連接點)又經組態以電連接至一電路面板，諸如一印刷電路板。在諸多習用設計中，晶片封裝佔據該電路面板之與晶片本身之面積相比相當大之一面積。如本發明中參考具有一前面之一扁平晶片所使用，應將「晶片之面積」理解為係指該前面之面積。
在「覆晶」設計中，晶片之前面面對一封裝介電元件(亦即，封裝之基板)之面，且晶片上之觸點係藉由焊料凸塊或其他連接元件而直接接合至該基板之面上之觸點。該基板又可透過上覆於該基板上之外部端子接合至一電路面 板。該「覆晶」設計提供一相對緊湊配置；每一封裝佔據該電路面板之等於或稍大於晶片之前面之面積的一面積，諸如在共同受讓之美國專利第5,148,265、5,148,266及5,679,977號之某些實施例中所揭示，該等專利之揭示內容以引用方式併入本文中。某些發明性安裝技術提供接近或等於習用覆晶接合之緊湊度的緊湊度。可將一單個晶片容納於電路面板之等於或稍大於晶片本身之面積的一面積中之封裝通常稱為「晶片級封裝」。
大小在任何晶片實體配置中皆係一重要考量。對於更緊湊晶片實體配置之需求已隨著可攜式電子裝置之迅速發展而變得甚至更強烈。僅以舉例方式，通常稱為「智慧電話」之裝置將一蜂巢式電話之功能與強大的資料處理器、記憶體及輔助裝置(諸如全球定位系統接收器、電子攝影機及區域網路連接)以及高解析度顯示器及相關聯影像處理晶片整合在一起。此等裝置可將諸如全網際網路連接性、包含全解析度視訊之娛樂、導航、電子銀行業務等等能力全部提供於一袖珍型裝置中。複雜的可攜式裝置需要將眾多晶片封裝至一小空間中。此外，該等晶片中之某些晶片具有通常稱為「I/O」之諸多輸入與輸出連接。此等I/O必須與其他晶片之I/O互連。形成該等互連之組件不應大大增加總成之大小。類似需要亦出現於其他應用中，如(舉例而言)在資料伺服器中，諸如用於網際網路搜尋引擎中之彼等資料伺服器，其中需要增加效能及大小減小。
含有記憶體儲存陣列之半導體晶片(尤其是動態隨機存 取記憶體晶片(DRAM)及快閃記憶體晶片)共同封裝於單晶片或多晶片封裝及總成中。每一封裝具有用於在端子與其中的晶片之間載運信號、電力及接地之諸多電連接。該等電連接可包含不同種類之導體，諸如相對於一晶片之一觸點承載表面沿一水平方向延伸之水平導體(例如，跡線、樑式引線等)，相對於晶片之該表面沿一垂直方向延伸之垂直導體(諸如導通體)，及相對於晶片之該表面沿水平方向及垂直方向兩者延伸之導線接合。
封裝內之信號至多晶片封裝之晶片之傳輸構成特別挑戰，尤其是對於封裝中之兩個或兩個以上晶片共同之信號(諸如時脈信號)及用於記憶體晶片之位址信號及選通信號而言。在此等多晶片封裝內，封裝之端子與晶片之間的連接路徑之長度可發生變化。不同的路徑長度可致使信號花費較長或較短時間以在端子與每一晶片之間行進。一信號自一個點至另一點之行進時間稱為「傳播延遲」，且隨導體長度、導體之結構及與其緊密接近之其他介電質或導體結構而變。
兩個不同信號到達一特定位置之時間差亦可稱為「扭斜」。一特定信號到達兩個或兩個以上位置之時間之扭斜係傳播延遲及該特定信號開始朝向該等位置行進之時間兩者之一結果。扭斜可或可不影響電路效能。在一同步信號群組中之所有信號一起扭斜時(於此情形中操作所需之所有信號在需要時一起到達)，扭斜通常對效能影響不大。然而，在操作所需之一同步信號群組中之不同信號在不同 時間處到達時並非如此。於此情形中，扭斜會影響效能，此乃因在所有需要的信號皆已到達之前不能執行操作。本文所述之實施例可包含最小化扭斜之特徵，其係闡述於同在申請中之美國臨時專利申請案第61/506,889號(TESSERA 3.8-664)中，該美國臨時專利申請案以引用的方式併入本文中。
習用微電子封裝可併入有經組態以主要提供記憶體儲存陣列功能之一微電子元件，亦即實現提供記憶體儲存陣列功能而非任何其他功能之較大數目個主動裝置之一微電子元件。該微電子元件可係一DRAM晶片或此等半導體晶片之一經堆疊電連接總成，或包含一DRAM晶片或此等半導體晶片之一經堆疊電連接總成。通常，此封裝之所有端子放置成毗鄰於該微電子元件安裝至其之一封裝基板之一或多個周邊邊緣之若干組行。
鑒於上文，可對多晶片微電子封裝及總成做出某些改良以便改良電效能。本發明之此等屬性可藉由如下文中所闡述之微電子封裝及總成之構造達成。
根據本發明之一態樣，一微電子封裝可包含：一基板，其具有第一與第二相對表面；第一、第二、第三及第四微電子元件；複數個端子，其等曝露於該第二表面處；及電連接，其等自每一微電子元件之觸點中之至少某些觸點延伸至該等端子中之至少某些端子。每一微電子元件可具有面向該基板之第一表面之一前表面，及在該前表面處之複 數個觸點。該等微電子元件之前表面可配置成平行於該第一表面且上覆於該第一表面上之一單個平面。每一微電子元件可具有曝露於該前表面處且沿著各別第一、第二、第三及第四軸配置之一行觸點。該第一軸與該第三軸可彼此平行。該第二軸及該第四軸可橫向於該第一軸及該第三軸。該等端子可組態用於將該微電子封裝連接至該微電子封裝外部之至少一個組件。
在一實例性實施例中，該第二軸及該第四軸可正交於該第一軸及該第三軸。在一特定實例中，每一微電子元件之該行觸點可安置於各別微電子元件之前表面之一中心區中。在一項實施例中，該等端子可配置成一區域陣列。該等端子可具有彼此共面之曝露接觸表面。在一特定實施例中，該等電連接可包含在該等下部微電子元件之每一者之觸點與曝露於該基板之第一表面處之導電接合墊之間延伸之覆晶連接。在一項實例中，每一微電子元件之觸點可包含八個資料I/O觸點。在一特定實例中，每一微電子元件之觸點可包含九個資料I/O觸點。在一特定實例中，每一微電子元件之觸點可包含十六個資料I/O觸點。
在一項實施例中，微電子封裝亦可包含電連接至該微電子封裝中之該等端子中之至少某些端子及該等微電子元件中之一或多者之一緩衝器元件。該緩衝器元件可經組態以重新產生在該微電子封裝之該等端子中之一或多者處接收之至少一個信號。在一特定實施例中，該緩衝器元件可係安裝至該基板之第一表面。在一項實例中，該緩衝器元件 可係安裝至基板之第二表面。在一特定實例中，該至少一個信號可包含傳送至該微電子封裝之所有位址信號。在一實例性實施例中，該至少一個信號可包含傳送至該微電子封裝之所有命令信號、位址信號、記憶體庫位址信號及時脈信號，該等命令信號係寫入啟用信號、列位址選通信號及行位址選通信號，且該等時脈信號係用於對位址信號取樣之取樣時脈。在一特定實施例中，該至少一個信號可包含由微電子封裝接收之所有資料信號。
在一項實例中，微電子封裝亦可包含安裝至該基板且經組態以儲存識別資訊之一非揮發性記憶體元件。該非揮發性記憶體元件可電連接至該等微電子元件中之一或多者。在一特定實例中，該微電子封裝亦可包含一溫度感測器。在一實例性實施例中，該微電子封裝亦可包含安裝至該基板之一去耦電容器元件。該去耦電容器元件可電連接至該等微電子元件中之一或多者。在一項實施例中，該基板可係基本上由在基板之一平面中具有小於12 ppm/C之一CTE之一材料構成之一元件。在一項實例中，該基板可包含基本上由在該基板之一平面中具有小於30 ppm/℃之一CTE之一材料構成之一介電元件。
在一特定實施例中，該等微電子元件可經組態以一起用作一可定址記憶體模組。該微電子封裝可經組態以儲存在該等微電子元件之每一者中接收之資料之部分。在一項實例中，該微電子封裝可經組態以用作一雙列直插記憶體模組。在一實例性實施例中，該微電子封裝可具有與一雙列 直插記憶體模組相同之命令及信號介面且可經組態以傳送與其相同的資料量。在一特定實例中，該等微電子元件之每一者可經組態以主要提供記憶體儲存陣列功能。在一項實施例中，該等微電子元件之每一者可包含一動態隨機存取記憶體(「DRAM」)積體電路晶片。在一特定實施例中，該等微電子元件之每一者可在功能上及機械上等效於該等微電子元件中之其他微電子元件。
在一實例性實施例中，該微電子封裝亦可包含與該等微電子元件之至少一者熱連通之一散熱片。在一項實例中，該散熱片可至少部分地上覆於該等微電子元件之每一者之一後表面上。在一特定實施例中，每一微電子元件可係一下部微電子元件，且每一微電子封裝可針對每一下部微電子元件包含一對應上部微電子元件。每一上部微電子元件可具有至少部分地上覆於該等下部微電子元件中之一對應下部微電子元件之一後表面上之一表面。在一項實施例中，該等上部微電子元件之至少一者可透過延伸穿過該等下部微電子元件中之一對應下部微電子元件之至少一個導電導通體與該下部微電子元件電連接。
根據本發明之一態樣，一微電子總成可包含如上文所述之複數個微電子封裝。該微電子總成亦可包含具有面板觸點之一電路面板。該封裝之端子可接合至該等面板觸點。在一項實施例中，該電路面板可具有用於往返於該等微電子封裝之每一者輸送信號之一共同電介面。在一特定實施例中，該等微電子封裝之每一者可經組態以具有與一雙列 直插記憶體模組相同之功能性。在一實例性實施例中，該電路面板可係一母板。在一項實例中，該電路面板可係經組態以附接至一母板之一模組。
在一特定實例中，該微電子總成亦可包含安裝至該電路面板且電連接至該等微電子封裝中之至少某些封裝之一緩衝器元件。該緩衝器元件可經組態以重新產生在該等微電子封裝之該等端子中之一或多者處接收之至少一個信號。在一特定實例中，該至少一個信號可包含傳送至該微電子總成之所有位址信號。在一項實施例中，該至少一個信號可包含傳送至微電子總成之所有命令信號、位址信號、記憶體庫位址信號及時脈信號，該等命令信號係寫入啟用信號、列位址選通信號及行位址選通信號，且該等時脈信號係用於對位址信號取樣之取樣時脈。在一實例性實施例中，該至少一個信號可包含由該微電子總成接收之所有資料信號。
根據本發明之一態樣，一模組可包含如上文所述之複數個微電子總成。每一微電子總成可電耦合至一第二電路面板，用於往返於該等微電子總成之每一者輸送信號。本發明之進一步態樣可提供併入有根據本發明之前述態樣之微電子總成、根據本發明之前述態樣之複合晶片、或兩者連同電連接至其之其他電子組件一起之系統。舉例而言，該系統可安置於可係一可攜式外殼之一單個外殼中。根據本發明之此態樣中之較佳實施例之系統可比相當的習用系統更緊湊。
根據本發明之另一態樣，一微電子封裝可包含：一基板，其具有第一與第二相對表面；第一、第二、第三及第四微電子元件；複數個端子，其等曝露於該第二表面處；及電連接，其等自每一微電子元件之觸點中之至少某些觸點延伸至該等端子中之至少某些端子。每一微電子元件可具有面向該基板之第一表面之一前表面及在該前表面處之複數個觸點。該等微電子元件之前表面可配置成平行於該第一表面且上覆於該第一表面上之一單個平面。每一微電子元件可至少部分地上覆於在該基板之第一表面與第二表面之間延伸之至少一個孔隙上。每一孔隙可具有沿著各別第一、第二、第三及第四軸之一長度。該第一軸與該第三軸可彼此平行。該第二軸及該第四軸可橫向於該第一軸及該第三軸。該等端子可組態用於將該微電子封裝連接至該微電子封裝外部之至少一個組件。該等電連接可包含至少具有與該至少一個孔隙對準之部分之引線。
在一項實例中，該等引線中之至少某些引線可包含延伸穿過該等孔隙之至少一者之導線接合。在一特定實施例中，所有引線皆可係延伸穿過該等孔隙之至少一者之導線接合。在一實例性實施例中，該等引線中之至少某些引線可包含引線接合。在一項實施例中，每一微電子元件之觸點中之至少某些觸點可在各別微電子元件之前表面之一中心區中安置成一行。在一特定實例中，每一微電子元件之該行觸點可與該等孔隙中之一對應孔隙對準。在一項實例中，該等孔隙之每一者可具有沿橫向於該各別軸之一方向 之一寬度，每一孔隙之寬度不大於沿與該孔隙之寬度相同之方向至少部分地上覆於該孔隙上之微電子元件之一寬度。在一項實施例中，基板之第二表面可具有佔據其一中心部分之一中心區。該中心區可由第一、第二、第三及第四軸定界。該等端子中之至少某些端子可係安置於中心區中之第一端子。
在一項實施例中，第一端子可經組態以載運傳送至微電子封裝之所有位址信號。在一特定實例中，第一端子可經組態以載運傳送至微電子封裝之命令信號、位址信號、記憶體庫位址信號及時脈信號中之至少某些信號，該等命令信號係寫入啟用信號、列位址選通信號及行位址選通信號，且該等時脈信號係用於對位址信號取樣之取樣時脈，該等第一端子係由該等微電子元件之至少兩者共用。在一項實施例中，該等第一端子可由該等微電子元件之每一者共用。
在一實例性實施例中，該微電子封裝亦可包含電連接至該微電子封裝中之該等端子中之至少某些端子及該等微電子元件中之一或多者之一緩衝器元件。該緩衝器元件可經組態以重新產生在該微電子封裝之該等端子中之一或多者處接收之至少一個信號。在一特定實例中，該緩衝器元件可安裝至該基板之第一表面。在一項實施例中，該緩衝器元件可安裝至該基板之第二表面。
本文之本發明實施例提供一種封裝或微電子總成，其中 一微電子元件(例如，一半導體晶片或半導體晶片之堆疊配置)經組態以主要提供一記憶體儲存陣列功能。在此微電子元件中，其中之經組態(亦即，經構造及與其他裝置互連)以提供記憶體儲存陣列功能之主動裝置(例如，電晶體)之數目大於經組態以提供任何其他功能之主動裝置之數目。因此，在一項實例中，諸如一DRAM晶片之一微電子元件可將記憶體儲存陣列功能作為其主要或唯一功能。另一選擇係，在另一實例中，此微電子元件可具有混合用途且可併入有經組態以提供記憶體儲存陣列功能之主動裝置，且亦可併入有經組態以提供另一功能(諸如處理器功能或信號處理器或圖形處理器功能以及其他功能)之其他主動裝置。於此情形中，微電子元件仍可具有經組態以提供記憶體儲存陣列功能而非任何其他功能之微電子元件之較大數目個主動裝置。
本發明之實施例提供其中具有一個以上半導體晶片(亦即，一微電子元件)之封裝。一多晶片封裝可減少將其中的晶片連接至一電路面板(例如，該封裝可透過諸如一球形柵格陣列(Ball Grid Array)、平台柵格陣列(Land Grid Array)或針形柵格陣列(Pin Grid Array)以及其他陣列之一端子陣列電連接及機械連接至之印刷佈線板)所需之面積或空間量。此連接空間在小型或可攜式計算裝置(例如，諸如「智慧電話」或平板電腦之手持式裝置，其通常組合個人電腦功能與對更寬廣世界之無線連接)中尤其受限。多晶片封裝可尤其有利於製作一系統可用之大量相對廉價 記憶體，諸如進階高效能動態隨機存取記憶體(「DRAM」)晶片，例如在DDR3型DRAM晶片及其後續產品中。
可藉由在封裝上提供共同端子來減少將多晶片封裝連接至其所需之電路面板之面積量，其中至少某些信號透過該等共同端子沿其軌跡行進至或自該封裝內之兩個或兩個以上晶片。然而，以支援高效能操作之一方式如此做會引發挑戰。為避免由於未終接之短截線所致的不期望效應(諸如信號之不期望反射)，將封裝外部處之端子與電路面板上之全域佈線電連接之在一電路面板上之跡線、導通體及其他導體必須不太長。散熱亦引發對進階晶片之一挑戰，因此每一晶片之大的扁平表面之至少一者耦合至一散熱片或曝露至一已安裝系統內之一流體或空氣或與其熱連通將係所期望的。下文所述之封裝可有助於推進此等目標。
圖1A至圖1C圖解說明根據本發明之一實施例之一特定類型之微電子封裝10。如圖1A至圖1C中所見，微電子封裝10可包含封裝結構，舉例而言，具有相對之第一表面21與第二表面22之一基板20。在某些情形中，基板20可沿基板之一平面(沿平行於基板之第一表面21之一方向)基本上由具有一低熱膨脹係數(「CTE」)(亦即小於每攝氏度每百萬(在下文中，「ppm/℃」)12部分之一CTE)之一材料構成，諸如一半導體材料(例如矽)或一介電材料(諸如陶瓷材料或二氧化矽，例如玻璃)。另一選擇係，基板20可包含一薄片狀基板，其基本上由一聚合材料構成，諸如聚醯亞 胺、環氧樹脂、熱塑性塑膠、熱固性塑膠或其他適合的聚合材料，或其包含或基本上由複合聚合-無機材料構成，諸如BT樹脂(雙馬來醯亞胺三嗪)之一玻璃強化結構或環氧樹脂玻璃(諸如FR-4)以及其他材料。在一項實例中，此一基板20可沿基板平面(亦即，按沿其表面之一方向)基本上由具有小於30 ppm/℃之一CTE之一材料構成。
在圖1A至圖1C中，平行於基板20之第一表面21之方向在本文中稱為「水平」或「橫向」方向，而垂直於該第一表面之方向在本文中稱為向上或向下方向且在本文中亦稱為「垂直」方向。本文中所提及之方向皆在所提及結構之參考框架中。因此，此等方向可在一重力參考框架中位於相對於正常「上」或「下」方向之任一定向處。
一個特徵安置於「一表面上方」大於另一特徵之一高度處之一陳述意指該一個特徵在比該另一特徵沿相同正交方向背離該表面一較大距離處。相反，一個特徵安置於「一表面上方」小於另一特徵之一高度處之一陳述意指該一個特徵在比該另一特徵沿相同正交方向背離該表面一較小距離處。
至少一個孔隙26可在基板20之第一表面21與第二表面22之間延伸。如在圖1A中可見，基板20可具有延伸穿過其之四個孔隙26。基板20可在其上具有複數個端子25，例如導電墊、連接盤(land)、或導電柱或導電針。此等端子25可曝露於基板20之第二表面22處。端子25可用作微電子封裝10與一外部組件之對應導電元件(諸如一電路面板(例如印 刷佈線板、撓性電路面板)、插座、另一微電子總成或封裝、插入件或被動組件總成以及其他元件(例如，圖8A中展示之電路面板))之連接之端點。在一項實例中，此一電路面板可係一母板或DIMM模組板。在一特定實施例中，端子可配置成一區域陣列，諸如一球形柵格陣列(BGA)(包含如下文所述之連結元件11)、一平台柵格陣列(LGA)、或一針形柵格陣列(PGA)以及其他陣列。在一項實施例中，端子25可沿著基板20之第二表面22之周邊配置。
在一實例性實施例中，端子25可包含由一導電材料(諸如銅、銅合金、金、鎳及類似材料)製成之實質上剛性柱。可藉由(舉例而言)將一導電材料植入至一抗蝕遮罩中之開口中、或藉由形成由(舉例而言)銅、銅合金、鎳或其組合製成之柱來形成端子25。此等柱可藉由(舉例而言)將一金屬薄片或其他金屬結構以減除方式圖案化成延伸離開基板20之柱作為端子而形成，用於電連接微電子封裝10與一外部組件(舉例而言，諸如下文所述之電路面板860)。如(舉例而言)美國專利第6,177,636號(其揭示內容以引用的方式併入本文中)中所闡述，端子25可係具有其他組態之實質上剛性柱。在一項實例中，端子25可具有彼此共面之曝露接觸表面。
微電子封裝10可包含附接至端子25用於與一外部組件連接之連結元件11。連結元件11可係(舉例而言)一種接合金屬(諸如焊料、錫、銦)、一共晶組合物或其組合之塊，或 係另一連結材料(諸如一導電膏或一導電膠)。在一特定實施例中，端子25與一外部組件(例如，圖8A中展示之電路面板860)之觸點之間的接頭可包含一導電矩陣材料，諸如在共同所有的美國專利申請案13/155,719及13/158,797中所闡述，該等專利申請案之揭示內容以引用的方式併入本文中。在一特定實施例中，該等接頭可具有一類似結構或可以如其中所述之一方式形成。
如本發明中所使用，一導電元件「曝露於」一結構之一表面「處」之一陳述指示該導電元件可用於與沿垂直於該表面之一方向自該結構外側朝向該表面移動之一理論點接觸。因此，曝露於一結構之一表面處之一端子或其他導電元件可自此表面突出；可與此表面齊平；或可相對於此表面凹入且透過該結構中之一孔或凹陷部曝露。
端子25可包含曝露於基板20之第二表面22之一中心區23中之第一端子25a及曝露於該中心區外側之第二表面之一周邊區28中之第二端子25b。圖1A至圖1C中展示之配置可在不要求一微電子元件上覆於任一其他微電子元件上之情況下提供微電子元件30及一相對廣闊之中心區23之一緊湊配置。
第一端子25a可經組態以載運自一外部組件傳送至微電子封裝10之所有命令信號、位址信號、記憶體庫位址信號及時脈信號。舉例而言，在包含一動態記憶體儲存陣列(例如，如一動態隨機存取記憶體(「DRAM」))之一微電子元件中，在此微電子元件係一動態隨機存取記憶體儲存 裝置時，命令信號係由微電子封裝10內之一微電子元件使用之寫入啟用信號、列位址選通信號及行位址選通信號。諸如ODT(晶粒上終止)、晶片選擇、時脈啟用之其他信號並非需要由第一端子25a載運之命令信號之部分。
時脈信號可係用於對位址信號取樣之取樣時脈。第二端子25b之至少某些端子可經組態以載運除命令信號、位址信號及時脈信號(其由第一端子25a載運)外的其他信號。第二端子25b可載運諸如晶片選擇、重設、電源電壓(例如，Vdd、Vddq)及接地電壓(例如，Vss及Vssq)之信號或參考電位；此等信號或參考電位皆無需由第一端子25a載運。
在一特定實例中，諸如圖1C中展示之實例，第二端子25b可在每一周邊區28中安置成至少一個行。在一項實施例中，經組態以載運除命令信號、位址信號及時脈信號外的其他信號之第二端子25b中之至少某些端子可曝露於基板20之第二表面22之中心區23中。
微電子封裝10亦可包含複數個微電子元件30，其各自具有面向基板20之第一表面21之一前表面31。在一項實例中，微電子元件30之每一者可係裸晶片或微電子單元，其各自併入有一記憶體儲存元件(諸如一動態隨機存取記憶體(「DRAM」)儲存陣列)或經組態以主要用作一DRAM儲存陣列(例如，一DRAM積體電路晶片)。如本文中所使用，一「記憶體儲存元件」係指配置成一陣列之眾多記憶體胞以及可用於儲存及自該等記憶體單元擷取資料(諸如用於經由一電介面之資料輸送)之電路。在一特定實例 中，微電子封裝10可包含於一單列直插記憶體模組(「SIMM」)或一雙列直插記憶體模組(「DIMM」)中。
在一特定實例中，包含一記憶體儲存元件之一微電子元件30可具有至少一記憶體儲存陣列功能，但該微電子元件亦可並非一全功能記憶體晶片。此一微電子元件本身可不具有一緩衝功能，但其可電連接至一微電子元件堆疊中之其他微電子元件，其中該堆疊中之至少一個微電子元件具有一緩衝功能(該緩衝微電子元件可係一緩衝器晶片、一全功能記憶體晶片或一控制器晶片)。
在其他實例中，本文所述封裝中之任一者中之微電子元件中之一或多者可實現提供記憶體儲存陣列功能而非任何其他功能之較大數目個主動裝置，例如作為快閃記憶體、DRAM或其他類型之記憶體，且可與經組態以主要提供邏輯功能之另一微電子元件或「邏輯晶片」一起配置於一封裝中。在一特定實施例中，該邏輯晶片可係一可程式化元件或處理器元件，諸如一微處理器或其他通用計算元件。該邏輯晶片可係一微控制器元件、圖形處理器、浮點處理器、共處理器、數位信號處理器等。在一特定實施例中，該邏輯晶片可主要執行硬體狀態機功能，或另外經硬編碼以起到一特定功能或目的。另一選擇係，該邏輯晶片可係一特殊應用積體電路(「ASIC」)或場可程式化閘陣列(「FPGA」)晶片。在此變化形式中，封裝則可係一「系統級封裝」(「SIP」)。
在另一變化形式中，本文所述封裝中之任一封裝中之一 微電子元件可在其中嵌入有邏輯功能及記憶體功能兩者，諸如在同一微電子元件中嵌入有一或多個相關聯記憶體儲存陣列之一可程式化處理器。此微電子元件有時稱為一「系統單晶片」(「SOC」)，此乃因邏輯件(諸如一處理器)係連同用於執行某一其他功能(其可係一特殊功能)之其他電路(諸如一記憶體儲存陣列或電路)一起嵌入。
在一特定實例中，微電子元件30之每一者可在功能上及機械上等效於該等微電子元件中之其他微電子元件，以使得每一微電子元件可在前表面31處具有帶相同功能之相同導電觸點35圖案，但每一微電子元件之長度、寬度及高度之特定尺寸可不同於其他微電子元件之彼等尺寸。
每一微電子元件30可具有曝露於其前表面31處之複數個導電觸點35。每一微電子元件30之觸點35可配置成一或多個行，安置於前表面31之一中心區36(佔據該前表面之一區域之一中心部分)中。舉例而言，中心區36可佔據前表面31之包含微電子元件30之相對周邊邊緣32a、32b之間的最短距離之中間三分之一的一區域。每一微電子元件30之前表面31可視為具有毗鄰一周邊邊緣32a之一第一周邊區、毗鄰另一周邊邊緣32b之一第二周邊區及安置於第一周邊區與第二周邊區之間的一中心區36。如圖1B中所展示，每一微電子元件30之觸點35可與孔隙26之至少一者對準。
如本文所使用，一微電子元件之一表面或面之中心區36(例如，一微電子元件30之前表面31)意指安置於表面之第 一周邊區與第二周邊區之間的表面之部分，該等周邊區毗鄰於微電子元件之各別第一及第二相對周邊邊緣(舉例而言，一微電子元件30之相對周邊邊緣32a、32b)安置，其中第一及第二周邊區與中心區之每一者具有等同寬度，以使得中心區佔據該表面之延伸此微電子元件之相對第一與第二周邊邊緣之間的最短距離之中間三分之一的一區域。
在一特定實施例中，微電子封裝10可具有四個微電子元件30，每一微電子元件之觸點35包含八個資料I/O觸點。在另一實施例中，微電子封裝10可具有四個微電子元件30，每一微電子元件之觸點35包含十六個資料I/O觸點。在一特定實例中，微電子封裝10(及本文所述之其他微電子封裝中之任一者)可經組態以在一時脈週期中並行傳送(亦即，由該封裝接收或自封裝傳輸)三十二個資料位元。在另一實例中，微電子封裝10(及本文所述之其他微電子封裝中之任一者)可經組態以在一時脈週期中並行傳送六十四個資料位元。若干其他資料傳輸數量亦係可能的，將在不加以限制之情況下提及當中的僅數個此等傳送數量。舉例而言，微電子封裝10(及本文所述之其他微電子封裝中之任一者)可經組態以傳送每時脈週期七十二個資料位元，其中可包含一組六十四個基礎位元(其表示資料)及八個位元(其係該六十四個基礎位元之錯誤校正碼(「ECC」)位元)。九十六個資料位元、108個位元(資料及ECC位元)、128個資料位元及144個位元(資料及ECC位元)係微電子封裝10(及本文所述之其他微電子封裝中之任一者)可經 組態以支援之每時脈資料傳送寬度之其他實例。
在圖1A至圖1C之實施例中，通過封裝之第一端子25a之至少某些信號可為微電子元件30之至少兩者共同所有。此等信號可透過沿平行於基板20之第二表面22之一方向自第一端子25a至微電子元件30之對應觸點35的連接(諸如導電跡線)來路由。微電子封裝10可透過該封裝之一共同第一端子25a而非透過各自專用於該等微電子元件中之特定一者之該封裝之兩個或兩個以上端子來路由多個微電子元件30共同所有的一信號。以此方式，可減少此等端子25所佔據之基板20之一面積量。
圖1A圖解說明在一基板20上之微電子元件30a、30b、30c及30d之一特定配置，類似於一風車之形狀。於此情形中，每一微電子元件30之複數個觸點35中之至少某些觸點可配置成一行各別觸點，定義各別第一軸29a、第二軸29b、第三軸29c及第四軸29d(統稱為軸29)。在圖1A中展示之實例中，第一軸29a與第三軸29c可彼此平行，第二軸29b與第四軸29d可彼此平行，且第一軸及第三軸可橫向於第二軸及第四軸。在一特定實施例中，第一軸29a及第三軸29c可正交於第二軸29b及第四軸29d。在一項實例中，第一軸29a、第二軸29b、第三軸29c及第四軸29d之每一者可由孔隙26a、26b、26c及26d中之一對應孔隙之一長度定義，以使得孔隙26可配置成如上文所述之一風車組態。
在圖1A中展示之特定實例中，每一微電子元件30之軸29可將各別微電子元件二等分且可橫穿微電子封裝10中之恰 好另一個微電子元件之區域。舉例而言，第一軸29a可將第一微電子元件30a二等分且可橫穿恰好另一個微電子元件30之區域。類似地，第二軸29b可將第二微電子元件30b二等分且可橫穿恰好另一個微電子元件30之區域。對第三軸29c而言同樣為真，其可將第三微電子元件30c二等分且可橫穿恰好另一個微電子元件30之區域。事實上，對第四軸29d而言此亦為真，其可將第四微電子元件30d二等分且可橫穿恰好另一個微電子元件30之區域。
觸點35與端子25之間的電連接可包含選用引線(例如，導線接合40)或其他可能結構，其中引線之至少部分與孔隙26之至少一者對準。舉例而言，如在圖1B中所見，該等電連接中之至少某些電連接可包含延伸超出基板中之一孔隙26之一邊緣且連結至基板之觸點35及一導電元件24之一導線接合40。在一項實施例中，該等電連接中之至少某些電連接可包含引線接合。此等連接可包含沿著基板20之第一表面21及第二表面22中之一者或兩者在導電元件24與端子25之間延伸的引線。在一特定實例中，此等引線可在每一微電子元件30之觸點35與端子25之間電連接，每一引線具有與孔隙26之至少一者對準之一部分。
在一項實例中，孔隙26之每一者可具有沿橫向於各別軸29之一方向之一寬度，每一孔隙之寬度不大於沿與孔隙寬度之方向相同的方向至少部分地上覆於該孔隙上之微電子元件30之一寬度。
在一項實例中，可將一或多個額外晶片30'安裝至基板 20，該一或多個額外晶片具有面向基板20之第一表面21(圖1A)或第二表面22之一表面31'。此一額外晶片30'可覆晶接合至曝露於基板20之第一表面21處之導電觸點。
額外晶片30'中之一或多者可係一緩衝晶片，其可經組態以幫助提供微電子元件30之每一者相對於微電子封裝10外部之組件之信號隔離。在一項實例中，此一緩衝晶片或緩衝元件可電連接至微電子封裝10中之端子25中之至少某些端子及微電子元件30中之一或多者，該緩衝器元件經組態以重新產生在微電子封裝10之該等端子中之一或多者處接收之至少一個信號。在一項實施例中，其中微電子封裝10係一具暫存器之DIMM，該至少一個信號可包含傳送至該封裝之所有命令信號、位址信號、記憶體庫位址信號及時脈信號，該等命令信號係寫入啟用信號、列位址選通信號及行位址選通信號，且該等時脈信號係用於對位址信號取樣之取樣時脈。在一特定實例中，在微電子封裝係一經減小負載之DIMM(「LRDIMM」)時，該至少一個信號可包含由微電子封裝接收之所有資料信號。
在一特定實施例中，額外晶片30'中之一或多者可係一去耦電容器。一或多個去耦電容器可安置於微電子元件30之間，替代或添加至前述緩衝晶片。此等去耦電容器可電連接至微電子封裝10內側之內部電力及接地匯流排。
在一項實施例中，額外晶片30'中之一者可係一非揮發性記憶體元件，諸如一電可抹除可程式化唯讀記憶體(「EEPROM」)，其安裝至基板20且經組態以主要儲存微 電子封裝10之識別資訊(諸如微電子封裝之資料寬度及深度)。此一非揮發性記憶體元件可電連接至微電子元件30中之一或多者。
在一項實例中，額外晶片30'中之一者可係一溫度感測器。此一溫度感測器可電連接至微電子元件30中之一或多者。在一項實例中，該溫度感測器可包含一個二極體且可安裝至基板20。在一特定實施例中，額外晶片30'中之一者可係安裝至基板20之一序列存在偵測元件。
微電子封裝10可進一步包含在微電子元件30之前表面31與基板20之第一表面21之間的一黏合劑12。微電子封裝10亦可包含可視情況覆蓋、部分覆蓋或完全不覆蓋微電子元件30之後表面32之一囊封材料(未展示)。舉例而言，在圖1A至圖1C中展示之封裝中，可將一囊封材料流動、模版印刷、絲網印刷或施配至微電子元件30之後表面32上。在另一實例中，該囊封材料可係藉由外模製而形成於其上之一模製合成物。
在上文所述實施例之變化形式中，微電子元件之觸點可能並不安置於其表面之中心區中。而是，該等觸點可安置於毗鄰此微電子元件之一邊緣之一或多個列中。在另一變化形式中，一微電子元件之觸點可安置於毗鄰此微電子元件之兩個相對邊緣處。在再一變化形式中，一微電子元件之觸點可安置於毗鄰任何兩個邊緣處，或安置於毗鄰此微電子元件之兩個以上邊緣處。在此等情形中，基板中之孔隙之位置可經修改以對應於安置於毗鄰該微電子元件之此 或此等邊緣處之觸點的此等位置。
圖2A及圖2B圖解說明上文相對於圖1A至圖1C所述之實施例之一變化形式，其中微電子元件230覆晶接合至基板220之第一表面221。在此一實施例中，微電子元件230與基板220之間的電連接包含在該等微電子元件之每一者之觸點與曝露於基板之第一表面221處之導電接合墊之間延伸之覆晶連接。
圖2C展示上文相對於圖2A及圖2B所述之實施例之一變化形式，其中微電子元件230中之一或多者係一下部微電子元件230'，且微電子封裝210'包含上部微電子元件230a、230b及230c，該等上部微電子元件各自具有至少部分地上覆於該下部微電子元件之一後表面232上之一表面。如圖2C中展示，上部微電子元件230a、230b及230c透過延伸穿過下部微電子元件之至少一個導電導通體209與下部微電子元件230'電連接。在一特定實施例中，下部微電子元件230"可導線接合至曝露於基板220之第二表面222處之導電觸點。
圖2D展示上文相對於圖2A及圖2B所述之實施例之一變化形式，其中微電子元件230中之一或多者係一下部微電子元件230"，且微電子封裝210"包含各自具有至少部分地上覆於該下部微電子元件之一後表面232上之一表面的上部微電子元件230a及230b。如圖2D中所展示，上部微電子元件230a及230b透過導線接合240與下部微電子元件230"電連接，其中導線接合240在上部微電子元件之觸點235與 曝露於下部微電子元件230"之後表面232處之導電元件245之間延伸。在一特定實施例中，下部微電子元件230"可導線接合至曝露於基板220之第二表面222處之導電觸點。
圖3A至圖3D展示在圖1A至圖1C中展示之微電子封裝10之額外變化形式，其中具有微電子元件相對於基板之第一表面之不同位置。在圖3A至圖3D中，各別微電子封裝301、302、303及304可各自包含四個微電子元件330，每一微電子元件具有透過一各別孔隙326導線接合至曝露於基板320之第二表面處之觸點。孔隙326可定義基板之第二表面之一中心區323之邊界之部分，其中可定位連接至微電子元件330之至少兩者之共用第一端子。
在圖3A中，微電子封裝301具有類似於圖1A至圖1C之微電子元件30配置之微電子元件330，但微電子元件330各自具有一實質上方形形狀，因此在定位於微電子元件之間的基板320之第一表面處存在極少空間。
在圖3B中，微電子元件330之每一者具有平行於各別孔隙326之一長度定向之第一邊緣332a及相對邊緣332b。微電子元件330之每一者之第一邊緣332a可定義不延伸穿過其他微電子元件中之任一者之區域之一軸329。在此一實施例中，在位於微電子元件330之間的基板320之第一表面處存在一較大空間，且基板之第二表面之中心區323可係相對大的。
在圖3C中，微電子元件330之每一者可上覆於一各別孔隙326上，該各別孔隙定義不延伸穿過其他微電子元件中 之任一者之區域之一軸329。然而，與圖3B相比，微電子元件330a及330c兩者已移動至較接近於基板320之第一表面之一中心處。微電子元件330之每一者具有平行於各別孔隙326之一長度定向之第一邊緣332a及相對邊緣332b。第一微電子元件330a及第三微電子元件330c之第一邊緣332a可定義延伸穿過第二微電子元件330b及第四微電子元件330d之區域之各別軸329a及329c。
圖3D係圖3C之一變化形式，其中微電子元件330a及330c兩者已移動至甚至更接近於基板320之第一表面之一中心處。第一微電子元件330a及第三微電子元件330b可上覆於一各別孔隙326a及326c上，該等各別孔隙定義延伸穿過第二微電子元件330b及第四微電子元件330d之區域之一各別軸329及329'。而且，微電子元件330之每一者具有平行於各別孔隙326之一長度定向之第一邊緣332a及相對邊緣332a。第一微電子元件330a及第三微電子元件330c之第一邊緣332a可定義亦延伸穿過第二微電子元件330b及第四微電子元件330d之區域之各別軸329a及329c。
圖4A及圖4B展示在圖1A至圖1C中展示之具有三個微電子元件之微電子封裝10之額外變化形式，該三個微電子元件具有配置成平行於基板420之第一表面之一單個平面之前表面。在圖4A中，微電子封裝401具有安裝至基板410之第一側之三個微電子元件430。微電子元件430a中之一第一者可具有(舉例而言)以諸如在圖2C或圖2D中展示之方式的一方式至少部分地上覆於第一微電子元件上且與其電連 接之額外微電子元件。舉例而言，微電子元件430b中之一第二者可係一控制器。在圖4B中，微電子封裝402與圖1A至圖1C中展示之微電子封裝10相同，但省略呈風車組態之微電子元件430中之一者，留下具有配置成平行於基板420之第一表面之一單個平面之前表面之三個微電子元件。
圖5A至圖5C圖解說明上文相對於圖1A至圖1C所述之實施例之一變化形式。微電子封裝510類似於圖1A至圖1C中展示之微電子封裝10。然而，封裝510含有多對507下部微電子元件530a與上部微電子元件530b。在每一此對507中，一上部微電子元件530b之前表面531至少部分地上覆於一下部微電子元件530a之一表面532上，表面532可係此下部微電子元件530a之後表面。毗鄰微電子元件對507(諸如一第一對507a及一第二對507b)可沿平行於基板520之第一表面521之一水平方向H彼此完全間隔開。在一特定實例中，微電子元件530a及530b可一起實現提供記憶體儲存陣列功能而非任何其他功能之較大數目個主動裝置。
在一項實施例中，微電子封裝510可具有八個微電子元件530(包含四個下部微電子元件530a及四個上部微電子元件530b)，每一微電子元件包含八個資料I/O觸點。在另一實施例中，微電子封裝510可具有八個微電子元件530(包含四個下部微電子元件530a及四個上部微電子元件530b)，每一微電子元件包含九個資料I/O觸點。
在一特定實例中，曝露於毗鄰微電子元件對之下部微電子元件530a之前表面531處之導電觸點535中之至少某些觸 點可配置成定義第一軸529a及第二軸529a'之各別行觸點。如圖5A中展示，此第一軸529a及第二軸529a'可橫向於彼此。在一特定實例中，第一軸529a及第二軸529a'可彼此正交。在一項實施例中，第一軸529a及第二軸529a'可彼此平行。
在一項實施例中，每一微電子元件對507可至少部分地上覆於在基板520之第一表面521與第二表面522之間延伸之一外部孔隙526a上。每一外部孔隙526a可具有沿平行於第一表面及第二表面之一方向延伸之一外部軸509a。四個外部軸509a可配置成如上文所述之一風車組態，其中外部軸509a可配置成兩對平行外部軸，每一對皆橫向於另一對。佔據基板520之第二表面522之一中心部分之一中心區523可由四個外部軸509a定界，如圖5C中所展示。曝露於基板520之第二表面522之中心區523處之端子525中之至少某些端子可係具有類似於上文所述之第一端子25a之一功能的第一端子。
在一實例性實施例中，每一微電子元件對507亦可至少部分地上覆於在基板520之第一表面521與第二表面522之間延伸之毗鄰同一微電子元件對中之外部孔隙526a中之一對應孔隙之一內部孔隙526b上，如圖5A中所展示。每一內部孔隙526b可具有定義沿平行於第一表面及第二表面之一方向延伸之一軸509b之一長度，每一內部軸509b比由外部孔隙526a中之對應外部孔隙之長度定義之軸509a更接近於基板之一形心501。
如圖5A中展示，每一下部微電子元件530a上覆於一外部孔隙526a上，且每一上部微電子元件530b上覆於一內部孔隙526b上。在一特定實施例中，每一上部微電子元件530b可上覆於一外部孔隙526a上，且每一下部微電子元件530a可上覆於一內部孔隙526b上。在一項實例中，下部微電子元件530a中之一或多者可上覆於對應外部孔隙526a上，且其他下部微電子元件可上覆於對應內部孔隙526b上，而上部微電子元件530b中之一或多者可上覆於對應外部孔隙上，且其他上部微電子元件可上覆於對應內部孔隙上。
在一特定實例中，每一上部微電子元件530b可上覆於一第一孔隙上，該第一孔隙可係一內部孔隙526b或一外部孔隙526a。該等第一孔隙之每一者可具有沿橫向於其長度之一方向之一寬度，第一孔隙之每一者之寬度不大於沿與第一孔隙之寬度相同之方向上覆於第一孔隙上之上部微電子元件530b中之對應上部微電子元件之一寬度。
在一項實例中，每一下部微電子元件530a可上覆於一第二孔隙上，該第二孔隙可係一內部孔隙526b或一外部孔隙526a。該等第二孔隙之每一者可具有沿橫向於其長度之一方向之一寬度，該等第二孔隙之每一者之寬度不大於沿與第二孔隙之寬度相同之方向上覆於第二孔隙上之下部微電子元件530a中之對應下部微電子元件之一寬度。
一間隔物514可定位於上部微電子元件530b之前表面531與基板520之第一表面521之一部分之間，具有或不具有定位於該間隔物與該基板之第一表面之間的一黏合劑512。 舉例而言，此一間隔物514可由一介電材料(諸如二氧化矽)、一半導體材料(諸如矽)或一或多個黏合劑層製成。若間隔物514包含黏合劑，則該等黏合劑可將上部微電子元件530b連接至基板520。在一項實施例中，間隔物514可沿實質上垂直於基板520之第一表面521之一垂直方向V具有與下部微電子元件530a之前表面531與後表面532之間的下部微電子元件530a之厚度T2實質上相同的厚度T1。在一特定實施例中，舉例而言，在間隔物514係由一黏合劑材料製成時，可在無需一黏合劑512(諸如上述黏合劑12)之情況下使用間隔物514。
圖6A至圖6C圖解說明上文相對於圖5A至圖5C所述之實施例之一變化形式。微電子封裝610類似於圖5A至圖5C中展示之微電子封裝510，但在微電子封裝610中，一上部微電子元件630b之前表面631至少部分地上覆於兩個下部微電子元件630a之一後表面632上。所有下部微電子元件630a可具有配置成平行於基板620之第一表面621之一單個平面之前表面631。
圖7圖解說明上文相對於圖5A至圖5C所述之實施例之另一變化形式。微電子封裝710與圖5A至圖5C中展示之微電子封裝510相同，但微電子封裝710包含三個微電子元件對707，每一對具有一下部微電子元件730a與一上部微電子元件730b。替代一第四微電子元件對707，微電子封裝710包含兩個下部微電子元件730a與一個對應上部微電子元件730b之一群組，其具有至少部分地上覆於該等上部微電子 元件之每一者之後表面732上之一前表面731。在一項實例中，微電子封裝710可具有各自包含八個資料I/O觸點之九個微電子元件730。
現在參照圖8A及圖8B，一微電子總成801可包含可安裝至一共同電路面板860之複數個微電子封裝810。微電子封裝810之每一者展示為來自圖1A至圖1C之一微電子封裝10，但此等微電子封裝810可係上文參照圖1A至圖7所述之微電子封裝中之任一者。電路面板860可具有相對之第一表面861與第二表面862及曝露於該等各別第一表面與第二表面處之複數個導電面板觸點。微電子封裝810可(舉例而言)藉由圖1B中展示之連結元件11(其可在每一微電子封裝之端子與面板觸點之間延伸)安裝至面板觸點。如圖8B中展示，一第一微電子封裝810a之基板之第二表面與一第二微電子封裝810b之基板之第二表面可至少部分地彼此上覆。在一特定實例中，電路面板860可包含具有小於30 ppm/℃之一CTE之一元件。在一項實施例中，此一元件可基本上由半導體、玻璃、陶瓷或液晶聚合物材料構成。
在一特定實施例中，電路面板860可具有毗鄰第一表面861及第二表面862之至少一者之一插入邊緣851之複數個平行的曝露邊緣觸點850，用於在將微電子總成801插入一插座(在圖9中展示)中時與該插座之對應觸點配對。該等邊緣觸點850中之某些或全部可曝露於微電子總成801之第一表面861或第二表面862中之一者或兩者處。在一項實例中，電路面板860可係一母板。在一實例性實施例中，電 路面板860可係可經組態以附接至另一電路面板(諸如一母板)之一模組(諸如一記憶體子系統)。電路面板860至另一電路面板之此附接可係如下文所述。
曝露邊緣觸點850及插入邊緣851可經調整大小以插入至一系統之其他連接器之一對應插座(圖9)，諸如可提供於一母板上。此等曝露邊緣觸點850可適合於與此插座連接器內之複數個對應彈簧觸點(圖9)配對。此等彈簧觸點可安置於每一槽之單側或多側上，以與曝露邊緣觸點850中之對應曝露邊緣觸點配對。在一項實例中，邊緣觸點850中之至少某些觸點可用於在各別邊緣觸點與微電子封裝810中之一或多者之間載運一信號或一參考電位之至少一者。在一特定實施例中，微電子總成801可具有與一雙列直插記憶體模組相同的信號介面。
圖8C至圖8E展示在圖8A及圖8B中展示之微電子總成801之變化形式，包含展示為來自圖5A至圖5C之微電子封裝510之微電子封裝810'。在圖8C中，微電子封裝802具有安裝至電路面板860之一第一側861之五個微電子封裝810'。
在圖8D中，微電子封裝803具有安裝至電路面板860之一第一表面861之五個微電子封裝810'，且諸如圖1A中展示之額外晶片30'之一額外晶片830'展示為具有面向電路面板之第一表面之一表面。此一額外晶片830'可係上文參照圖1A至圖1C所述之額外晶片類型中之任一者，包含(舉例而言)可經組態以有助於為微電子封裝810'之每一者相對於微電子總成803外部之組件提供信號隔離之一緩衝晶片。在 一項實例中，額外晶片830'可包含一記憶體控制器。
在圖8E中，微電子封裝804具有各自安裝至一各別插座805之五個微電子封裝810'，且每一插座安裝至電路面板860之第一表面861。
上文參照圖1至圖8E闡述之微電子封裝及微電子總成可用於多種多樣之電子系統之構造中，諸如圖9中展示之系統900。舉例而言，根據本發明之又一實施例之系統900包含複數個模組或組件906，諸如如上文結合其他電子組件908及910闡述之微電子封裝及微電子總成。
系統900可包含複數個插座905，每一插座包含在插座之一側或兩側處之複數個觸點907，以使得每一插座905可適合於與一對應模組或組件906之對應曝露邊緣觸點或曝露模組觸點配對。在所展示之實例性系統900中，系統可包含一電路面板或母板902，諸如一撓性印刷電路板，且電路面板可包含使模組或組件906彼此互連之大量導體904，其中在圖9中僅繪示其一者。此一電路面板902可往返於系統900中所包含之微電子封裝10或110之每一者輸送信號。然而，此僅係實例性的；可使用用於在模組或組件906之間進行電連接之任一適合結構。在一特定實例中，可將模組或組件906(諸如微電子封裝10)中之一或多者直接安裝至電路面板902，而非將模組或組件906透過插座905耦合至電路面板902。
在一特定實施例中，系統900亦可包含一處理器(諸如半導體晶片908)，以使得每一模組或組件906可經組態以在 一時脈週期中並行傳送N數目個資料位元，且處理器可經組態以在一時脈週期中並行傳送M數目個資料位元，M大於或等於N。
在一項實例中，系統900可包含一處理器晶片908，該處理器晶片經組態以在一時鐘週期中並行傳送三十二個資料位元，且該系統亦可包含四個模組906，諸如參照圖1A至圖1C闡述之模組10，每一模組906經組態以在一時鐘週期中並行傳送八個資料位元(亦即，每一模組906可包含第一微電子元件及第二微電子元件，該兩個微電子元件之每一者經組態以在一時鐘週期中並行傳送四個資料位元)。
在另一實例中，系統900可包含一處理器晶片908，該處理器晶片經組態以在一時鐘週期中並行傳送六十四個資料位元，且該系統亦可包含四個模組906，諸如參照圖9所述之組件1000，每一模組906經組態以在一時鐘週期中並行傳送十六個資料位元(亦即，每一模組906可包含兩組第一及第二微電子元件，該四個微電子元件之每一者經組態以在一時鐘週期中並行傳送四個資料位元)。
在圖9中繪示之實例中，組件908係一半導體晶片，且組件910係一顯示器螢幕，但在系統900中亦可使用任一其他組件。當然，儘管為清楚地圖解說明而在圖9中繪示僅兩個額外組件908及910，但系統900可包含任一數目個此等組件。
模組或組件906與組件908及910可安裝於一共同外殼901中(以虛線示意性地繪示)，且可視需要彼此電互連以形成 所期望之電路。外殼901繪示為可用於(舉例而言)一蜂巢式電話或個人數位助理中之類型之一可攜式外殼，且螢幕910可曝露於該外殼之表面處。在結構906包含一光敏元件(諸如一成像晶片)之實施例中，亦可提供一透鏡911或其他光學裝置以將光路由至該結構。同樣，圖9中所展示之簡化系統僅係實例性的；可使用上文所論述之結構來製作其他系統，包含通常被視為固定結構之系統，諸如桌上型電腦、路由器及諸如此類。
在前述微電子封裝中之任一者或全部中，在完成製造之後該等微電子元件中之一或多者之後表面可至少部分地曝露於微電子封裝之一外部表面處。因此，在上文參照圖1A闡述之微電子封裝10中，微電子元件30之後表面32可部分地或完全地曝露於完成之微電子封裝10中之一囊封材料之一外部表面處。
在上述實施例中之任一者中，微電子封裝可包含部分地或整個地由任一適合導熱材料製成之一散熱片。適合之導熱材料之實例包含但不限於金屬、石墨、導熱膠(例如，導熱環氧樹脂)、一焊料或諸如此類、或此等材料之一組合。在一項實例中，散熱片可係一實質上連續之金屬薄片。
在一項實施例中，散熱片可包含安置於毗鄰於該等微電子元件中之一或多者處之一金屬層。該金屬層可曝露於微電子封裝之一後表面處。另一選擇係，該散熱片可包含覆蓋該微電子元件之至少後表面之一外模製件或一囊封材 料。在一項實例中，該散熱片可與微電子元件之每一者之前表面及後表面之至少一者熱連通，諸如圖1A及圖1B中展示之微電子元件30。該散熱片可在該等微電子元件中之毗鄰者之毗鄰邊緣之間延伸。該散熱片可改良對周圍環境之熱耗散。
在一特定實施例中，由金屬或另一導熱材料製成之一預製散熱片可藉助一導熱材料(諸如導熱膠或導熱脂)附接至或安置於該等微電子元件中之一或多者之後表面上。該黏合劑(若存在)可係一順應材料，其准許散熱片與其附接至之微電子元件之間的相對移動以(舉例而言)容納順應附接元件之間的不同熱膨脹。該散熱片可係一單片結構。另一選擇係，該散熱片可包含彼此間隔開之多個散熱片部分。在一特定實施例中，該散熱片可係或可包含一焊料層，該焊料層直接連結至微電子元件中之一或多者之一後表面之至少一部分，諸如圖1A及圖1B中展示之微電子元件30。
儘管已參考特定實施例闡述了本發明，但應理解，此等實施例僅圖解說明本發明之原理及應用。因此，應理解，可對例示性實施例作出眾多修改且可設想出其他配置，而此並不背離隨附申請專利範圍所定義之本發明之精神及範疇。
應瞭解，本文中所陳述之各種隨附請求項及特徵可以不同於初始請求項中所呈現之方式來組合。亦應瞭解，結合個別實施例所闡述之特徵可與所闡述實施例中之其他實施例共用。
1B-1B‧‧‧線
2B-2B‧‧‧線
5B-5B‧‧‧線
6B-6B‧‧‧線
10‧‧‧微電子封裝
11‧‧‧連結元件
12‧‧‧黏合劑
20‧‧‧基板
21‧‧‧第一表面
22‧‧‧第二表面
23‧‧‧中心區
24‧‧‧導電元件
25‧‧‧端子
25a‧‧‧第一端子
25b‧‧‧第二端子
26‧‧‧孔隙
26a‧‧‧孔隙
26b‧‧‧孔隙
26c‧‧‧孔隙
26d‧‧‧孔隙
28‧‧‧周邊區
29a‧‧‧第一軸
29b‧‧‧第二軸
29c‧‧‧第三軸
29d‧‧‧第四軸
30‧‧‧微電子元件
30'‧‧‧額外晶片
30a‧‧‧微電子元件/第一微電子元件
30b‧‧‧微電子元件/第二微電子元件
30c‧‧‧微電子元件/第三微電子元件
30d‧‧‧微電子元件/第四微電子元件
31‧‧‧前表面
32‧‧‧後表面
32a‧‧‧周邊邊緣
32b‧‧‧周邊邊緣
35‧‧‧導電觸點/觸點
36‧‧‧中心區
40‧‧‧導線接合
209‧‧‧導電導通體
210'‧‧‧微電子封裝
210"‧‧‧微電子封裝
220‧‧‧基板
221‧‧‧第一表面
222‧‧‧第二表面
230‧‧‧微電子元件
230'‧‧‧下部微電子元件
230"‧‧‧下部微電子元件
230a‧‧‧上部微電子元件
230b‧‧‧上部微電子元件
230c‧‧‧上部微電子元件
232‧‧‧後表面
235‧‧‧觸點
240‧‧‧導線接合
245‧‧‧導電元件
301‧‧‧微電子封裝
302‧‧‧微電子封裝
303‧‧‧微電子封裝
304‧‧‧微電子封裝
320‧‧‧基板
323‧‧‧中心區
326‧‧‧孔隙
326a‧‧‧孔隙
326c‧‧‧孔隙
329‧‧‧軸
329a‧‧‧軸
329c‧‧‧軸
329'‧‧‧軸
330‧‧‧微電子元件
330a‧‧‧微電子元件/第一微電子元件
330b‧‧‧微電子元件/第二微電子元件
330c‧‧‧微電子元件/第三微電子元件
330d‧‧‧微電子元件/第四微電子元件
332a‧‧‧第一邊緣
332b‧‧‧相對邊緣
401‧‧‧微電子封裝
402‧‧‧微電子封裝
420‧‧‧基板
430‧‧‧微電子元件
430a‧‧‧微電子元件
430b‧‧‧微電子元件
501‧‧‧形心
507a‧‧‧第一對
507b‧‧‧第二對
509a‧‧‧外部軸/軸
509b‧‧‧內部軸/軸
510‧‧‧微電子封裝/封裝
512‧‧‧黏合劑
514‧‧‧間隔物
520‧‧‧基板
521‧‧‧第一表面
523‧‧‧中心區
525‧‧‧端子
526a‧‧‧外部孔隙
526b‧‧‧內部孔隙
529a‧‧‧第一軸
529a'‧‧‧第二軸
530a‧‧‧下部微電子元件/微電子元件
530b‧‧‧上部微電子元件/微電子元件
531‧‧‧前表面
532‧‧‧表面/後表面
535‧‧‧導電觸點
610‧‧‧微電子封裝
620‧‧‧基板
621‧‧‧第一表面
630a‧‧‧下部微電子元件
630b‧‧‧上部微電子元件
707‧‧‧對/第四對
710‧‧‧微電子封裝
730a‧‧‧下部微電子元件
730b‧‧‧上部微電子元件
801‧‧‧微電子總成
802‧‧‧微電子封裝
803‧‧‧微電子總成/微電子封裝
804‧‧‧微電子封裝
805‧‧‧插座
810‧‧‧微電子封裝
810'‧‧‧微電子封裝
810a‧‧‧第一微電子封裝
810b‧‧‧第二微電子封裝
830'‧‧‧額外晶片
850‧‧‧曝露邊緣觸點/邊緣觸點
851‧‧‧插入邊緣
860‧‧‧電路面板
861‧‧‧第一表面/第一側
862‧‧‧第二表面
900‧‧‧系統
901‧‧‧外殼
902‧‧‧電路面板/母板
904‧‧‧導體
905‧‧‧插座
906‧‧‧模組或組件/模組/結構
907‧‧‧觸點
908‧‧‧電子組件/半導體晶片/處理器晶片/組件/額外組件
910‧‧‧電子組件/組件/額外組件/螢幕
911‧‧‧透鏡
H‧‧‧水平方向
T1‧‧‧間隔物厚度
T2‧‧‧下部微電子元件厚度
V‧‧‧垂直方向
圖1A係根據本發明之一實施例之一微電子封裝之一概略透視圖。
圖1B係沿著圖1A之線1B-1B截取之圖1A之微電子封裝之一側剖視圖。
圖1C係展示微電子元件之位置之圖1A之微電子封裝之一仰視圖。
圖2A係根據具有覆晶安裝至一基板之微電子元件之另一實施例之一微電子封裝之一概略透視圖。
圖2B係沿著圖2A之線2B-2B截取之圖2A之微電子封裝之一側剖視圖。
圖2C及圖2D係圖2A之微電子封裝之變化形式(具有至少部分地上覆於對應下部微電子元件上之一或多個上部微電子元件)之側剖視圖。
圖3A至圖3D係根據進一步實施例具有四個微電子元件之微電子封裝之俯視圖，展示接合窗及中心區之位置。
圖4A及圖4B係根據再其他實施例具有三個微電子元件之微電子封裝之俯視圖，展示接合窗及中心區之位置。
圖5A係根據具有堆疊之微電子元件之又一實施例之一微電子封裝之一概略透視圖。
圖5B係沿著圖5A之線5B-5B截取之圖5A之微電子封裝之一側剖視圖。
圖5C係圖5A之微電子封裝之一仰視圖，展示微電子元件之位置。
圖6A係根據具有堆疊之微電子元件之又一實施例之一微電子封裝之一概略透視圖。
圖6B係沿著圖6A之線6B-6B截取之圖6A之微電子封裝之一側剖視圖。
圖6C係圖6A之微電子封裝之一仰視圖，展示微電子元件之位置。
圖7係根據具有堆疊之微電子元件之再一實施例之一微電子封裝之一概略透視圖。
圖8A係具有安裝至一電路面板之複數個微電子封裝之一微電子總成之一概略透視圖。
圖8B係圖8A之微電子總成之一仰視圖。
圖8C至圖8E係根據具有安裝至一電路面板之複數個微電子封裝之進一步實施例之微電子總成之概略透視圖。
圖9係根據包含複數個模組之一項實施例之一系統之一示意性繪圖。
1B-1B‧‧‧線
10‧‧‧微電子封裝
20‧‧‧基板
21‧‧‧第一表面
22‧‧‧第二表面
26‧‧‧孔隙
26a‧‧‧孔隙
26b‧‧‧孔隙
26c‧‧‧孔隙
26d‧‧‧孔隙
29a‧‧‧第一軸
29b‧‧‧第二軸
29c‧‧‧第三軸
29d‧‧‧第四軸
30‧‧‧微電子元件
30'‧‧‧額外晶片
30a‧‧‧微電子元件/第一微電子元件
30b‧‧‧微電子元件/第二微電子元件
30c‧‧‧微電子元件/第三微電子元件
30d‧‧‧微電子元件/第四微電子元件
32‧‧‧後表面

Claims (39)

  1. 一種微電子封裝，其包括：一基板，其具有第一與第二相對表面；第一、第二、第三及第四微電子元件，每一微電子元件具有面向該基板之該第一表面之一前表面及在該前表面處之複數個觸點，該等微電子元件之該等前表面配置成平行於該第一表面且上覆於該第一表面上之一單個平面，每一微電子元件具有曝露於該前表面處且沿著各別第一、第二、第三及第四軸配置之一行觸點，該第一軸與該第三軸彼此平行，該第二軸及該第四軸橫向於該第一軸及該第三軸，其中每一微電子元件之該行觸點係安置於各別微電子元件之該前表面之一中心區中；複數個端子，其等曝露於該第二表面處，該等端子經組態用於將該微電子封裝連接至該微電子封裝外部之至少一個組件；及電連接，其等自每一微電子元件之該等觸點中之至少某些觸點延伸至該等端子中之至少某些端子。
  2. 如請求項1之微電子封裝，其中該第二軸及該第四軸正交於該第一軸及該第三軸。
  3. 如請求項1之微電子封裝，其中該等端子配置成一區域陣列，該等端子具有彼此共面之曝露接觸表面。
  4. 如請求項1之微電子封裝，其中該等電連接包含在下部微電子元件之每一者之觸點與曝露於該基板之該第一表面處之導電接合墊之間延伸之覆晶連接。
  5. 如請求項1之微電子封裝，其中每一微電子元件之該等觸點包含八個資料I/O觸點。
  6. 如請求項1之微電子封裝，其中每一微電子元件之該等觸點包含九個資料I/O觸點。
  7. 如請求項1之微電子封裝，其中每一微電子元件之該等觸點包含十六個資料I/O觸點。
  8. 如請求項1之微電子封裝，其進一步包括電連接至該微電子封裝中之該等端子中之至少某些端子及該等微電子元件中之一或多者之一緩衝器元件，該緩衝器元件經組態以重新產生在該微電子封裝之該等端子中之一或多者處接收之至少一個信號。
  9. 如請求項8之微電子封裝，其中該緩衝器元件係安裝至該基板之該第一表面。
  10. 如請求項8之微電子封裝，其中該緩衝器元件係安裝至該基板之該第二表面。
  11. 如請求項8之微電子封裝，其中該至少一個信號包含傳送至該微電子封裝之所有位址信號。
  12. 如請求項8之微電子封裝，其中該至少一個信號包含傳送至該微電子封裝之所有命令信號、位址信號、記憶體庫位址信號及時脈信號，該等命令信號係寫入啟用信號、列位址選通信號及行位址選通信號，且該等時脈信號係用於對該等位址信號取樣之取樣時脈。
  13. 如請求項8之微電子封裝，其中該至少一個信號包含由該微電子封裝接收之所有資料信號。
  14. 如請求項1之微電子封裝，其進一步包括安裝至該基板且經組態以儲存識別資訊之一非揮發性記憶體元件，該非揮發性記憶體元件電連接至該等微電子元件中之一或多者。
  15. 如請求項1之微電子封裝，其進一步包括一溫度感測器。
  16. 如請求項1之微電子封裝，其進一步包括安裝至該基板之一去耦電容器元件，該去耦電容器元件電連接至該等微電子元件中之一或多者。
  17. 如請求項1之微電子封裝，其中該基板係基本上由在該基板之一平面中具有小於12ppm/℃之一CTE之一材料構成之一元件。
  18. 如請求項1之微電子封裝，其中該基板包含基本上由在該基板之一平面中具有小於30ppm/℃之一CTE之一材料構成之一介電元件。
  19. 如請求項1之微電子封裝，其中該等微電子元件經組態以一起用作一可定址記憶體模組，該微電子封裝經組態以儲存在該等微電子元件之每一者中接收之資料之部分。
  20. 如請求項19之微電子封裝，其中該微電子封裝經組態以用作一雙列直插記憶體模組。
  21. 如請求項20之微電子封裝，其中該微電子封裝具有與一雙列直插記憶體模組相同之命令及信號介面且經組態以傳送與該雙列直插記憶體模組相同之資料量。
  22. 如請求項1之微電子封裝，其中該等微電子元件之每一者經組態以主要提供記憶體儲存陣列功能。
  23. 如請求項1之微電子封裝，其中該等微電子元件之每一者包含一動態隨機存取記憶體(「DRAM」)積體電路晶片。
  24. 如請求項1之微電子封裝，其中該等微電子元件之每一者在功能上及機械上等效於該等微電子元件中之其他微電子元件。
  25. 如請求項1之微電子封裝，其進一步包括與該等微電子元件之至少一者熱連通之一散熱片。
  26. 如請求項25之微電子封裝，其中該散熱片至少部分地上覆於該等微電子元件之每一者之一後表面上。
  27. 如請求項1之微電子封裝，其中每一微電子元件係一下部微電子元件，且每一微電子封裝針對每一下部微電子元件包含一對應上部微電子元件，每一上部微電子元件具有至少部分地上覆於該等下部微電子元件中之該對應下部微電子元件之一後表面上之一表面。
  28. 如請求項27之微電子封裝，其中該等上部微電子元件之至少一者透過延伸穿過該等下部微電子元件中之一對應下部微電子元件之至少一個導電導通體與該下部微電子元件電連接。
  29. 一種包含如請求項1之複數個微電子封裝之微電子總成，該微電子總成進一步包括具有面板觸點之一電路面板，其中該封裝之端子接合至該等面板觸點。
  30. 如請求項29之微電子總成，其中該電路面板具有用於往返於該等微電子封裝之每一者輸送信號之一共同電介面。
  31. 如請求項29之微電子總成，其中該等微電子封裝之每一者經組態以具有與一雙列直插記憶體模組相同之功能性。
  32. 如請求項29之微電子總成，其中該電路面板係一母板。
  33. 如請求項29之微電子總成，其中該電路面板係經組態以附接至一母板之一模組。
  34. 如請求項29之微電子總成，其進一步包括安裝至該電路面板且電連接至該等微電子封裝中之至少某些微電子封裝之一緩衝器元件，該緩衝器元件經組態以重新產生在該等微電子封裝之該等端子中之一或多者處接收之至少一個信號。
  35. 如請求項34之微電子總成，其中該至少一個信號包含傳送至該微電子總成之所有命令信號、位址信號、記憶體庫位址信號及時脈信號，該等命令信號係寫入啟用信號、列位址選通信號及行位址選通信號，且該等時脈信號係用於對該等位址信號取樣之取樣時脈。
  36. 如請求項34之微電子總成，其中該至少一個信號包含由該微電子總成接收之所有資料信號。
  37. 一種包含如請求項29之複數個微電子總成之模組，每一微電子總成電耦合至一第二電路面板，用於往返於該等微電子總成之每一者輸送信號。
  38. 一種微電子系統，其包括如請求項1之一微電子封裝及電連接至該微電子封裝之一或多個其他電子組件。
  39. 如請求項38之微電子系統，其進一步包括一外殼，該微電子封裝及該等其他電子組件係安裝至該外殼。
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