JP2014521222A - パッケージ内のメモリモジュール - Google Patents
パッケージ内のメモリモジュール Download PDFInfo
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- JP2014521222A JP2014521222A JP2014520276A JP2014520276A JP2014521222A JP 2014521222 A JP2014521222 A JP 2014521222A JP 2014520276 A JP2014520276 A JP 2014520276A JP 2014520276 A JP2014520276 A JP 2014520276A JP 2014521222 A JP2014521222 A JP 2014521222A
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- microelectronic
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
Abstract
【選択図】図1A
Description
本出願は、2012年1月9日に出願された米国特許出願第13/346,201号の継続出願である。この米国特許出願は、全てが2011年10月3日に出願された米国仮特許出願第61/542,488号、第61/542,495号、及び第61/542,553号と、2011年7月12日に出願された米国仮特許出願第61/506,889号との出願日の利益を主張する。これらの米国仮特許出願の開示内容は、引用することによって本明細書の一部をなすものとする。
Claims (54)
- 超小型電子パッケージであって、
対向する第1の表面及び第2の表面を有する基板と、
第1の超小型電子素子、第2の超小型電子素子、第3の超小型電子素子、及び第4の超小型電子素子であって、各超小型電子素子は、前記基板の前記第1の表面の方に向いた前面と、該前面における複数のコンタクトとを有し、該超小型電子素子の前記前面は、前記第1の表面に対して平行であるとともに前記第1の表面の上に重なる単一の平面内に配置され、各超小型電子素子は、前記前面に露出するとともにそれぞれの第1の軸、第2の軸、第3の軸、及び第4の軸に沿って配置されたコンタクトの列を有し、前記第1の軸及び前記第3の軸は互いに平行であり、前記第2の軸及び前記第4の軸は、前記第1の軸及び前記第3の軸に対して横向きである、第1の超小型電子素子、第2の超小型電子素子、第3の超小型電子素子、及び第4の超小型電子素子と、
前記第2の表面に露出した複数の端子であって、該端子は、該超小型電子パッケージの外部の少なくとも1つの構成要素に該超小型電子パッケージを接続するように構成されている、複数の端子と、
各超小型電子素子の前記コンタクトのうちの少なくとも幾つかから前記端子のうちの少なくとも幾つかに延在する電気的接続部と
を備えてなる、超小型電子パッケージ。 - 前記第2の軸及び前記第4の軸は、前記第1の軸及び前記第3の軸に対して直交している、請求項1に記載の超小型電子パッケージ。
- 各超小型電子素子の前記コンタクトの列は、前記それぞれの超小型電子素子の前記前面の中央領域に配置されている、請求項1に記載の超小型電子パッケージ。
- 前記端子は、エリアアレイに配置され、前記端子は、互いに同一平面上にある露出した接触面を有する、請求項1に記載の超小型電子パッケージ。
- 前記電気的接続部は、下側超小型電子素子のそれぞれのコンタクトと、前記基板の前記第1の表面に露出した導電性ボンドパッドとの間に延在するフリップチップ接続部を含む、請求項1に記載の超小型電子パッケージ。
- 各超小型電子素子の前記コンタクトは、8つのデータI/Oコンタクトを含む、請求項1に記載の超小型電子パッケージ。
- 各超小型電子素子の前記コンタクトは、9つのデータI/Oコンタクトを含む、請求項1に記載の超小型電子パッケージ。
- 各超小型電子素子の前記コンタクトは、16個のデータI/Oコンタクトを含む、請求項1に記載の超小型電子パッケージ。
- 請求項1に記載の超小型電子パッケージであって、該超小型電子パッケージにおいて、前記端子のうちの少なくとも幾つかと、前記超小型電子素子のうちの1つ以上のものとに電気的に接続されたバッファ素子を更に備え、該バッファ素子は、該超小型電子パッケージの前記端子のうちの1つ以上のものにおいて受信された少なくとも1つの信号を再生成するように構成されている、請求項1に記載の超小型電子パッケージ。
- 前記バッファ素子は、前記基板の前記第1の表面に実装される、請求項9に記載の超小型電子パッケージ。
- 前記バッファ素子は、前記基板の前記第2の表面に実装される、請求項9に記載の超小型電子パッケージ。
- 前記少なくとも1つの信号は、該超小型電子パッケージに転送されるアドレス信号の全てを含む、請求項9に記載の超小型電子パッケージ。
- 前記少なくとも1つの信号は、該超小型電子パッケージに転送されるコマンド信号、アドレス信号、バンクアドレス信号、及びクロック信号の全てを含み、前記コマンド信号は、書き込みイネーブル信号、行アドレスストローブ信号、及び列アドレスストローブ信号であり、前記クロック信号は、前記アドレス信号をサンプリングするのに用いられるサンプリングクロックである、請求項9に記載の超小型電子パッケージ。
- 前記少なくとも1つの信号は、該超小型電子パッケージによって受信されたデータ信号の全てを含む、請求項9に記載の超小型電子パッケージ。
- 前記基板に実装されるとともに識別情報を記憶するように構成された不揮発性メモリ素子を更に備え、該不揮発性メモリ素子は、前記超小型電子素子のうちの1つ以上のものに電気的に接続されている、請求項1に記載の超小型電子パッケージ。
- 温度センサを更に備える、請求項1に記載の超小型電子パッケージ。
- 前記基板に実装されたデカップリングコンデンサ素子を更に備え、該デカップリングコンデンサ素子は、前記超小型電子素子のうちの1つ以上のものに電気的に接続されている、請求項1に記載の超小型電子パッケージ。
- 前記基板は、該基板の平面における熱膨張係数が12ppm/℃未満である材料から基本的になる要素である、請求項1に記載の超小型電子パッケージ。
- 前記基板は、該基板の平面における熱膨張係数が30ppm/℃未満である材料から基本的になる誘電体素子を備える、請求項1に記載の超小型電子パッケージ。
- 前記超小型電子素子は、アドレス指定可能メモリモジュールとしてともに機能するように構成され、該超小型電子パッケージは、前記超小型電子素子のそれぞれにおいて受信されたデータの一部を記憶するように構成されている、請求項1に記載の超小型電子パッケージ。
- 請求項20に記載の超小型電子パッケージであって、該超小型電子パッケージは、デュアルインラインメモリモジュールとして機能するように構成されている、請求項20に記載の超小型電子パッケージ。
- 請求項21に記載の超小型電子パッケージであって、該超小型電子パッケージは、同じコマンド及び信号インタフェースを有し、デュアルインラインメモリモジュールと同じ量のデータを転送するように構成されている、請求項21に記載の超小型電子パッケージ。
- 前記超小型電子素子のそれぞれは、主としてメモリ記憶アレイ機能を提供するように構成されている、請求項1に記載の超小型電子パッケージ。
- 前記超小型電子素子のそれぞれは、ダイナミックランダムアクセスメモリ(「DRAM」)集積回路チップを含む、請求項1に記載の超小型電子パッケージ。
- 前記超小型電子素子のそれぞれは、該超小型電子素子のうちの他のものと機能的及び機械的に同等である、請求項1に記載の超小型電子パッケージ。
- 前記超小型電子素子のうちの少なくとも1つと熱連通する放熱体を更に備える、請求項1に記載の超小型電子パッケージ。
- 前記放熱体は、前記超小型電子素子のそれぞれの背面の上に少なくとも部分的に重なる、請求項26に記載の超小型電子パッケージ。
- 各超小型電子素子は、下側超小型電子素子であり、各超小型電子パッケージは、各下側超小型電子素子に対応する上側超小型電子素子を備え、各上側超小型電子素子は、前記下側超小型電子素子のうちの前記対応するものの背面の上に少なくとも部分的に重なる表面を有する、請求項1に記載の超小型電子パッケージ。
- 前記上側超小型電子素子のうちの少なくとも1つは、前記下側超小型電子素子を貫通して延在する少なくとも1つの導電性ビアを通じて、前記下側超小型電子素子のうちの対応するものと電気的に接続されている、請求項28に記載の超小型電子パッケージ。
- 請求項1に記載の複数の超小型電子パッケージを備える超小型電子アセンブリであって、パネルコンタクトを有する回路パネルを更に備え、前記パッケージの前記端子は、前記パネルコンタクトにボンディングされる、請求項1に記載の複数の超小型電子パッケージを備える超小型電子アセンブリ。
- 前記回路パネルは、前記超小型電子パッケージのそれぞれに及びそれぞれから信号をトランスポートする共通の電気インタフェースを有する、請求項30に記載の超小型電子アセンブリ。
- 前記超小型電子パッケージのそれぞれは、デュアルインラインメモリモジュールと同じ機能を有するように構成されている、請求項30に記載の超小型電子アセンブリ。
- 前記回路パネルはマザーボードである、請求項30に記載の超小型電子アセンブリ。
- 前記回路パネルは、マザーボードに取り付けられるように構成されたモジュールである、請求項30に記載の超小型電子アセンブリ。
- 前記回路パネルに実装されるとともに前記超小型電子パッケージのうちの少なくとも幾つかに電気的に接続されたバッファ素子を更に備え、該バッファ素子は、前記超小型電子パッケージの前記端子のうちの1つ以上のものにおいて受信された少なくとも1つの信号を再生成するように構成されている、請求項30に記載の超小型電子アセンブリ。
- 前記少なくとも1つの信号は、該超小型電子アセンブリに転送されるコマンド信号、アドレス信号、バンクアドレス信号、及びクロック信号の全てを含み、前記コマンド信号は、書き込みイネーブル信号、行アドレスストローブ信号、及び列アドレスストローブ信号であり、前記クロック信号は、前記アドレス信号をサンプリングするのに用いられるサンプリングクロックである、請求項35に記載の超小型電子アセンブリ。
- 前記少なくとも1つの信号は、該超小型電子アセンブリによって受信されたデータ信号の全てを含む、請求項35に記載の超小型電子アセンブリ。
- 各超小型電子アセンブリは、該超小型電子アセンブリのそれぞれに及びそれぞれから信号をトランスポートする第2の回路パネルに電気的に結合されている、請求項30に記載の複数の超小型電子アセンブリを備えるモジュール。
- 請求項1に記載の超小型電子パッケージと、該超小型電子パッケージに電気的に接続された1つ以上の他の電子構成要素とを備える、システム。
- ハウジングを更に備え、前記超小型電子パッケージ及び前記他の電子構成要素が該ハウジングに実装されている、請求項39に記載のシステム。
- 超小型電子パッケージであって、
対向する第1の表面及び第2の表面を有する基板と、
第1の超小型電子素子、第2の超小型電子素子、第3の超小型電子素子、及び第4の超小型電子素子であって、各超小型電子素子は、前記基板の前記第1の表面の方に向いた前面と、該前面における複数のコンタクトとを有し、該超小型電子素子の前記前面は、前記第1の表面に対して平行であるとともに前記第1の表面の上に重なる単一の平面内に配置され、各超小型電子素子は、前記基板の前記第1の表面と前記第2の表面との間に延在する少なくとも1つの開口部の上に少なくとも部分的に重なり、各開口部は、それぞれの第1の軸、第2の軸、第3の軸、及び第4の軸に沿った長さを有し、前記第1の軸及び前記第3の軸は互いに平行であり、前記第2の軸及び前記第4の軸は、前記第1の軸及び前記第3の軸に対して横向きである、第1の超小型電子素子、第2の超小型電子素子、第3の超小型電子素子、及び第4の超小型電子素子と、
前記第2の表面に露出した複数の端子であって、該端子は、前記超小型電子パッケージを該超小型電子パッケージの外部の少なくとも1つの構成要素に接続するように構成されている、複数の端子と、
各超小型電子素子の前記コンタクトのうちの少なくとも幾つかから前記端子のうちの少なくとも幾つかに延在する電気的接続部であって、少なくとも、前記少なくとも1つの開口部と位置合わせされた部分を有するリードを含む、電気的接続部と
を備えてなる、超小型電子パッケージ。 - 前記リードのうちの少なくとも幾つかは、前記開口部のうちの少なくとも1つを通って延在するワイヤボンドを含む、請求項41に記載の超小型電子パッケージ。
- 前記リードの全てが、前記開口部のうちの少なくとも1つを通って延在するワイヤボンドである、請求項41に記載の超小型電子パッケージ。
- 前記リードのうちの少なくとも幾つかは、リードボンドを含む、請求項41に記載の超小型電子パッケージ。
- 各超小型電子素子の前記コンタクトのうちの前記少なくとも幾つかは、前記それぞれの超小型電子素子の前記前面の中央領域において列に配置される、請求項41に記載の超小型電子パッケージ。
- 各超小型電子素子の前記コンタクトの列は、前記開口部のうちの対応するものと位置合わせされている、請求項45に記載の超小型電子パッケージ。
- 前記開口部のそれぞれは、前記それぞれの軸に対して横向きの方向に幅を有し、各開口部の前記幅は、該開口部の前記幅と同じ方向において、該開口部の上に少なくとも部分的に重なる前記超小型電子素子の幅よりも大きくない、請求項41に記載の超小型電子パッケージ。
- 前記基板の前記第2の表面は、その中央部分を占有する中央領域を有し、該中央領域は、前記第1の軸、前記第2の軸、前記第3の軸、及び前記第4の軸によって画定され、前記端子のうちの少なくとも幾つかは、前記中央領域に配置された第1の端子である、請求項41に記載の超小型電子パッケージ。
- 前記第1の端子は、該超小型電子パッケージに転送されるアドレス信号の全てを搬送するように構成されている、請求項48に記載の超小型電子パッケージ。
- 前記第1の端子は、該超小型電子パッケージに転送されるコマンド信号、アドレス信号、バンクアドレス信号、及びクロック信号のうちの少なくとも幾つかを搬送するように構成され、前記コマンド信号は、書き込みイネーブル信号、行アドレスストローブ信号、及び列アドレスストローブ信号であり、前記クロック信号は、前記アドレス信号をサンプリングするのに用いられるサンプリングクロックであり、前記第1の端子は、前記超小型電子素子のうちの少なくとも2つによって共有される、請求項48に記載の超小型電子パッケージ。
- 前記第1の端子は、前記超小型電子素子のそれぞれによって共有される、請求項50に記載の超小型電子パッケージ。
- 請求項41に記載の超小型電子パッケージであって、該超小型電子パッケージにおいて、前記端子のうちの少なくとも幾つかと、前記超小型電子素子のうちの1つ以上のものとに電気的に接続されたバッファ素子を更に備え、該バッファ素子は、該超小型電子パッケージの前記端子のうちの1つ以上のものにおいて受信された少なくとも1つの信号を再生成するように構成されている、請求項41に記載の超小型電子パッケージ。
- 前記バッファ素子は、前記基板の前記第1の表面に実装される、請求項52に記載の超小型電子パッケージ。
- 前記バッファ素子は、前記基板の前記第2の表面に実装される、請求項52に記載の超小型電子パッケージ。
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- 2012-01-09 US US13/346,201 patent/US8513817B2/en active Active
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- 2012-07-11 JP JP2014520276A patent/JP2014521222A/ja active Pending
- 2012-07-11 KR KR1020147003032A patent/KR20140054019A/ko active IP Right Grant
- 2012-07-11 WO PCT/US2012/046249 patent/WO2013009866A2/en active Application Filing
- 2012-07-11 CN CN201280044482.XA patent/CN103797574A/zh active Pending
- 2012-07-12 TW TW104114019A patent/TW201530541A/zh unknown
- 2012-07-12 TW TW101125191A patent/TWI488183B/zh not_active IP Right Cessation
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TW201308329A (zh) | 2013-02-16 |
WO2013009866A2 (en) | 2013-01-17 |
TW201530541A (zh) | 2015-08-01 |
CN103797574A (zh) | 2014-05-14 |
US8513817B2 (en) | 2013-08-20 |
KR20140054019A (ko) | 2014-05-08 |
WO2013009866A3 (en) | 2013-05-16 |
EP2732463A2 (en) | 2014-05-21 |
US20130015591A1 (en) | 2013-01-17 |
TWI488183B (zh) | 2015-06-11 |
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