JP4014708B2 - 半導体集積回路装置の設計方法 - Google Patents

半導体集積回路装置の設計方法 Download PDF

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Publication number
JP4014708B2
JP4014708B2 JP33833797A JP33833797A JP4014708B2 JP 4014708 B2 JP4014708 B2 JP 4014708B2 JP 33833797 A JP33833797 A JP 33833797A JP 33833797 A JP33833797 A JP 33833797A JP 4014708 B2 JP4014708 B2 JP 4014708B2
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Japan
Prior art keywords
cell
circuit
substrate potential
supply wiring
power supply
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Expired - Fee Related
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JP33833797A
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English (en)
Japanese (ja)
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JPH11126827A (ja
JPH11126827A5 (enExample
Inventor
隆嗣 柴田
茂 島田
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Renesas Technology Corp
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Renesas Technology Corp
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Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP33833797A priority Critical patent/JP4014708B2/ja
Priority to TW087111072A priority patent/TW463361B/zh
Priority to US09/131,393 priority patent/US6340825B1/en
Priority to KR1019980032981A priority patent/KR100544266B1/ko
Publication of JPH11126827A publication Critical patent/JPH11126827A/ja
Priority to US09/939,699 priority patent/US6611943B2/en
Priority to US09/947,507 priority patent/US6462978B2/en
Priority to US10/440,162 priority patent/US6912697B2/en
Publication of JPH11126827A5 publication Critical patent/JPH11126827A5/ja
Priority to US11/167,648 priority patent/US7541647B2/en
Priority to KR1020050080016A priority patent/KR100614557B1/ko
Application granted granted Critical
Publication of JP4014708B2 publication Critical patent/JP4014708B2/ja
Priority to US12/467,370 priority patent/US7642601B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP33833797A 1997-08-21 1997-12-09 半導体集積回路装置の設計方法 Expired - Fee Related JP4014708B2 (ja)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP33833797A JP4014708B2 (ja) 1997-08-21 1997-12-09 半導体集積回路装置の設計方法
TW087111072A TW463361B (en) 1997-08-21 1998-07-08 Semiconductor integrated circuit designing method and semiconductor integrated circuit
US09/131,393 US6340825B1 (en) 1997-08-21 1998-08-07 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device
KR1019980032981A KR100544266B1 (ko) 1997-08-21 1998-08-14 반도체집적회로의설계방법및반도체집적회로
US09/939,699 US6611943B2 (en) 1997-08-21 2001-08-28 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device
US09/947,507 US6462978B2 (en) 1997-08-21 2001-09-07 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device
US10/440,162 US6912697B2 (en) 1997-08-21 2003-05-19 Semiconductor integrated circuit device
US11/167,648 US7541647B2 (en) 1997-08-21 2005-06-28 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device
KR1020050080016A KR100614557B1 (ko) 1997-08-21 2005-08-30 반도체 집적회로장치
US12/467,370 US7642601B2 (en) 1997-08-21 2009-05-18 Method of designing semiconductor integrated circuit device and semiconductor integrated circuit device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP9-224560 1997-08-21
JP22456097 1997-08-21
JP33833797A JP4014708B2 (ja) 1997-08-21 1997-12-09 半導体集積回路装置の設計方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2005001324A Division JP2005175505A (ja) 1997-08-21 2005-01-06 半導体集積回路装置

Publications (3)

Publication Number Publication Date
JPH11126827A JPH11126827A (ja) 1999-05-11
JPH11126827A5 JPH11126827A5 (enExample) 2005-02-03
JP4014708B2 true JP4014708B2 (ja) 2007-11-28

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JP33833797A Expired - Fee Related JP4014708B2 (ja) 1997-08-21 1997-12-09 半導体集積回路装置の設計方法

Country Status (4)

Country Link
US (6) US6340825B1 (enExample)
JP (1) JP4014708B2 (enExample)
KR (2) KR100544266B1 (enExample)
TW (1) TW463361B (enExample)

Families Citing this family (130)

* Cited by examiner, † Cited by third party
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