DE69517693T2 - Standardzellenbibliothek für den Entwurf von integrierten Schaltungen - Google Patents
Standardzellenbibliothek für den Entwurf von integrierten SchaltungenInfo
- Publication number
- DE69517693T2 DE69517693T2 DE69517693T DE69517693T DE69517693T2 DE 69517693 T2 DE69517693 T2 DE 69517693T2 DE 69517693 T DE69517693 T DE 69517693T DE 69517693 T DE69517693 T DE 69517693T DE 69517693 T2 DE69517693 T2 DE 69517693T2
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuit
- circuit design
- standard cell
- cell library
- library
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP95830559A EP0782187B1 (de) | 1995-12-29 | 1995-12-29 | Standardzellenbibliothek für den Entwurf von integrierten Schaltungen |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69517693D1 DE69517693D1 (de) | 2000-08-03 |
DE69517693T2 true DE69517693T2 (de) | 2001-03-01 |
Family
ID=8222097
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69517693T Expired - Fee Related DE69517693T2 (de) | 1995-12-29 | 1995-12-29 | Standardzellenbibliothek für den Entwurf von integrierten Schaltungen |
Country Status (3)
Country | Link |
---|---|
US (1) | US5763907A (de) |
EP (1) | EP0782187B1 (de) |
DE (1) | DE69517693T2 (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4014708B2 (ja) * | 1997-08-21 | 2007-11-28 | 株式会社ルネサステクノロジ | 半導体集積回路装置の設計方法 |
JP3349989B2 (ja) * | 1999-06-18 | 2002-11-25 | エヌイーシーマイクロシステム株式会社 | 半導体集積回路装置及びそのレイアウト方法及び装置 |
EP1085333B1 (de) * | 1999-09-14 | 2005-07-13 | STMicroelectronics S.r.l. | Verfahren zur ruhestrombestimmung |
US6425115B1 (en) * | 2000-05-09 | 2002-07-23 | Ess Technology, Inc. | Area efficient delay circuits |
US6490708B2 (en) | 2001-03-19 | 2002-12-03 | International Business Machines Corporation | Method of integrated circuit design by selection of noise tolerant gates |
US7299203B1 (en) * | 2001-04-19 | 2007-11-20 | Xilinx, Inc. | Method for storing and shipping programmable ASSP devices |
AU2003223746A1 (en) * | 2002-04-25 | 2003-11-10 | Arc International | Apparatus and method for managing integrated circuit designs |
US7219324B1 (en) * | 2003-06-02 | 2007-05-15 | Virage Logic Corporation | Various methods and apparatuses to route multiple power rails to a cell |
US20050278659A1 (en) * | 2004-05-27 | 2005-12-15 | Xiaonan Zhang | Cell library providing transistor size information for automatic circuit design |
US7114134B2 (en) * | 2004-05-27 | 2006-09-26 | Veri Silicon Holdings, Co. Ltd | Automatic circuit design method with a cell library providing transistor size information |
US7254802B2 (en) * | 2004-05-27 | 2007-08-07 | Verisilicon Holdings, Co. Ltd. | Standard cell library having cell drive strengths selected according to delay |
JP2007103607A (ja) * | 2005-10-03 | 2007-04-19 | Matsushita Electric Ind Co Ltd | スタンダードセル、半導体集積回路、半導体集積回路の設計方法、半導体集積回路の設計装置、及びスタンダードセルライブラリ |
US7989849B2 (en) * | 2006-11-15 | 2011-08-02 | Synopsys, Inc. | Apparatuses and methods for efficient power rail structures for cell libraries |
JP2008213243A (ja) * | 2007-03-02 | 2008-09-18 | Ricoh Co Ltd | 光走査装置、光走査方法、プログラム、記録媒体及び画像形成装置 |
US8032338B2 (en) * | 2008-06-13 | 2011-10-04 | Power Integrations, Inc. | Method and apparatus for design of a power supply |
US8390331B2 (en) | 2009-12-29 | 2013-03-05 | Nxp B.V. | Flexible CMOS library architecture for leakage power and variability reduction |
US8423946B1 (en) | 2010-05-25 | 2013-04-16 | Marvell International Ltd. | Circuitry having programmable power rails, architectures, apparatuses, and systems including the same, and methods and algorithms for programming and/or configuring power rails in an integrated circuit |
US9529953B2 (en) * | 2012-08-02 | 2016-12-27 | The United States Of America, As Represented By The Secretary Of The Navy | Subthreshold standard cell library |
US10103258B2 (en) * | 2016-12-29 | 2018-10-16 | Texas Instruments Incorporated | Laterally diffused metal oxide semiconductor with gate poly contact within source window |
DE102017127276A1 (de) * | 2017-08-30 | 2019-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Standardzellen und abwandlungen davon innerhalb einer standardzellenbibliothek |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3983619A (en) * | 1968-01-26 | 1976-10-05 | Hitachi, Ltd. | Large scale integrated circuit array of unit cells and method of manufacturing same |
US5545904A (en) * | 1986-01-17 | 1996-08-13 | Quick Technologies Ltd. | Personalizable gate array devices |
JP2739958B2 (ja) * | 1988-06-28 | 1998-04-15 | 株式会社東芝 | スタンダードセル |
JPS6331644A (ja) * | 1986-07-25 | 1988-02-10 | 横河メディカルシステム株式会社 | X線断層撮影装置 |
JP2704534B2 (ja) * | 1988-12-16 | 1998-01-26 | 日本電信電話株式会社 | アナログ・デジタル混在lsi |
JPH0383375A (ja) * | 1989-08-25 | 1991-04-09 | Sony Corp | 半導体装置 |
US5164811A (en) * | 1990-04-20 | 1992-11-17 | Seiko Epson Corporation | Semiconductor integrated circuit with varying channel widths |
EP0471535B1 (de) * | 1990-08-13 | 1998-01-28 | Nec Corporation | Halbleiterspeicheranordnung |
US5384472A (en) * | 1992-06-10 | 1995-01-24 | Aspec Technology, Inc. | Symmetrical multi-layer metal logic array with continuous substrate taps and extension portions for increased gate density |
US5367187A (en) * | 1992-12-22 | 1994-11-22 | Quality Semiconductor, Inc. | Master slice gate array integrated circuits with basic cells adaptable for both input/output and logic functions |
JPH0758301A (ja) * | 1993-08-13 | 1995-03-03 | Oki Electric Ind Co Ltd | 半導体集積回路装置 |
JP3286470B2 (ja) * | 1994-08-09 | 2002-05-27 | 三菱電機株式会社 | 半導体集積回路、半導体集積回路の製造方法及びセルの配置方法 |
US5635737A (en) * | 1994-09-23 | 1997-06-03 | Aspec Technology, Inc. | Symmetrical multi-layer metal logic array with extension portions for increased gate density and a testability area |
-
1995
- 1995-12-29 EP EP95830559A patent/EP0782187B1/de not_active Expired - Lifetime
- 1995-12-29 DE DE69517693T patent/DE69517693T2/de not_active Expired - Fee Related
-
1996
- 1996-12-12 US US08/763,937 patent/US5763907A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
DE69517693D1 (de) | 2000-08-03 |
EP0782187B1 (de) | 2000-06-28 |
EP0782187A1 (de) | 1997-07-02 |
US5763907A (en) | 1998-06-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69517693D1 (de) | Standardzellenbibliothek für den Entwurf von integrierten Schaltungen | |
DE69616081D1 (de) | Verbindungsschema für integrierte schaltungen | |
DE69127060D1 (de) | Tester für integrierte Schaltungen | |
DE69621011D1 (de) | Kondensator für eine integrierte schaltung | |
DE69626441D1 (de) | Speicherentwurf für IC-Anschlüsse | |
DE68924452D1 (de) | Packungsstruktur für integrierte Schaltungen. | |
DE69525421D1 (de) | Integrierte Speicherschaltungsanordnung | |
DE69624160D1 (de) | Verbinderanordnung für integrierte Schaltungskarte | |
DE69615910D1 (de) | Schalter-Kondensator-Schnittstellenschaltung | |
DE69720725D1 (de) | Verbesserte Ausgangsschaltung für integrierte Schaltungen | |
DE69616464T2 (de) | Elektronisches prüfbares System | |
DE69611632D1 (de) | Planare Isolation für integrierte Schaltungen | |
DE69832007D1 (de) | Steuerschaltung für Computerspeicher | |
DE69631384T2 (de) | Verbesserungen an chipkarten | |
DE69600633T2 (de) | Eingangsschaltung für Halbleiterspeicher | |
DE69630018D1 (de) | Logische schaltung für niedrige spannungen | |
DE69610737T2 (de) | Bondflächen-Option für integrierte Schaltungen | |
DE3855949D1 (de) | Gehäuse für integrierte Schaltungen | |
DE69034048D1 (de) | Planare Isoliertechnik für integrierte Schaltungen | |
DE69509037D1 (de) | Entwicklungsanordnung | |
DE69413459T2 (de) | Speicherschaltung für parallelen Datenausgang | |
DE69724708D1 (de) | Verbesserungen betreffend integrierte Schaltungen | |
DE69304722D1 (de) | TTL-CMOS-Ausgangsstufe für integrierte Schaltungen | |
DE69622172T2 (de) | Integrierte schaltungsanordnung | |
KR970705918A (ko) | 회로 배열(Circuit arrangement) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |