DE69616081D1 - Verbindungsschema für integrierte schaltungen - Google Patents
Verbindungsschema für integrierte schaltungenInfo
- Publication number
- DE69616081D1 DE69616081D1 DE69616081T DE69616081T DE69616081D1 DE 69616081 D1 DE69616081 D1 DE 69616081D1 DE 69616081 T DE69616081 T DE 69616081T DE 69616081 T DE69616081 T DE 69616081T DE 69616081 D1 DE69616081 D1 DE 69616081D1
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuits
- connection scheme
- scheme
- connection
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/532,915 US5834845A (en) | 1995-09-21 | 1995-09-21 | Interconnect scheme for integrated circuits |
PCT/US1996/013931 WO1997011488A1 (en) | 1995-09-21 | 1996-08-30 | Interconnect scheme for integrated circuits |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69616081D1 true DE69616081D1 (de) | 2001-11-22 |
DE69616081T2 DE69616081T2 (de) | 2002-07-11 |
Family
ID=24123729
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69616081T Expired - Lifetime DE69616081T2 (de) | 1995-09-21 | 1996-08-30 | Verbindungsschema für integrierte schaltungen |
Country Status (6)
Country | Link |
---|---|
US (1) | US5834845A (de) |
EP (1) | EP0852065B1 (de) |
JP (1) | JP2001515654A (de) |
KR (1) | KR100451110B1 (de) |
DE (1) | DE69616081T2 (de) |
WO (1) | WO1997011488A1 (de) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09283751A (ja) * | 1996-04-11 | 1997-10-31 | Toshiba Corp | 半導体装置およびその製造方法 |
US5990507A (en) | 1996-07-09 | 1999-11-23 | Kabushiki Kaisha Toshiba | Semiconductor device having ferroelectric capacitor structures |
US6049132A (en) * | 1996-07-12 | 2000-04-11 | Kawasaki Steel Corporation | Multiple metallization structure for a reflection type liquid crystal display |
US6576848B1 (en) * | 1996-11-22 | 2003-06-10 | International Business Machines Corporation | Integrated circuit chip wiring structure with crossover capability and method of manufacturing the same |
JP3340333B2 (ja) * | 1996-12-26 | 2002-11-05 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6037248A (en) * | 1997-06-13 | 2000-03-14 | Micron Technology, Inc. | Method of fabricating integrated circuit wiring with low RC time delay |
US6731007B1 (en) * | 1997-08-29 | 2004-05-04 | Hitachi, Ltd. | Semiconductor integrated circuit device with vertically stacked conductor interconnections |
US5969421A (en) * | 1997-11-18 | 1999-10-19 | Lucent Technologies Inc. | Integrated circuit conductors that avoid current crowding |
US5977571A (en) * | 1998-02-26 | 1999-11-02 | Lucent Technologies, Inc. | Low loss connecting arrangement for photodiodes |
JP3515363B2 (ja) * | 1998-03-24 | 2004-04-05 | 株式会社東芝 | 半導体装置の製造方法 |
US6303988B1 (en) * | 1998-04-22 | 2001-10-16 | Packard Hughes Interconnect Company | Wafer scale burn-in socket |
FR2779274B1 (fr) * | 1998-05-27 | 2000-08-18 | St Microelectronics Sa | Circuit integre avec couche d'arret et procede de fabrication associe |
JP3378505B2 (ja) * | 1998-06-23 | 2003-02-17 | 株式会社東芝 | 半導体装置およびその製造方法 |
FR2782838A1 (fr) * | 1998-08-25 | 2000-03-03 | St Microelectronics Sa | Procede de fabrication d'un circuit integre et circuit integre en technique double damascene auto aligne |
EP0989609B1 (de) * | 1998-09-25 | 2005-02-09 | STMicroelectronics S.r.l. | Verbindungsstruktur in mehreren Ebenen |
US6171945B1 (en) * | 1998-10-22 | 2001-01-09 | Applied Materials, Inc. | CVD nanoporous silica low dielectric constant films |
US6965165B2 (en) | 1998-12-21 | 2005-11-15 | Mou-Shiung Lin | Top layers of metal for high performance IC's |
TW408435B (en) * | 1998-12-31 | 2000-10-11 | Taiwan Semiconductor Mfg | Self aligned process and structure capable of increasing the yield of borderless contact window |
JP2001024056A (ja) * | 1999-07-12 | 2001-01-26 | Mitsubishi Electric Corp | 半導体装置の多層配線装置及びその製造方法 |
US6399983B1 (en) * | 1999-09-02 | 2002-06-04 | Micron Technology, Inc. | Reduction of shorts among electrical cells formed on a semiconductor substrate |
US6875687B1 (en) | 1999-10-18 | 2005-04-05 | Applied Materials, Inc. | Capping layer for extreme low dielectric constant films |
EP1094506A3 (de) | 1999-10-18 | 2004-03-03 | Applied Materials, Inc. | Schutzschicht für Filme mit besonders kleiner Dielektrizitätskonstante |
US6428942B1 (en) * | 1999-10-28 | 2002-08-06 | Fujitsu Limited | Multilayer circuit structure build up method |
US6869750B2 (en) * | 1999-10-28 | 2005-03-22 | Fujitsu Limited | Structure and method for forming a multilayered structure |
US6882045B2 (en) * | 1999-10-28 | 2005-04-19 | Thomas J. Massingill | Multi-chip module and method for forming and method for deplating defective capacitors |
US6165891A (en) | 1999-11-22 | 2000-12-26 | Chartered Semiconductor Manufacturing Ltd. | Damascene structure with reduced capacitance using a carbon nitride, boron nitride, or boron carbon nitride passivation layer, etch stop layer, and/or cap layer |
US6483176B2 (en) * | 1999-12-22 | 2002-11-19 | Kabushiki Kaisha Toshiba | Semiconductor with multilayer wiring structure that offer high speed performance |
US6284657B1 (en) | 2000-02-25 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | Non-metallic barrier formation for copper damascene type interconnects |
US7265062B2 (en) * | 2000-04-04 | 2007-09-04 | Applied Materials, Inc. | Ionic additives for extreme low dielectric constant chemical formulations |
US6576568B2 (en) | 2000-04-04 | 2003-06-10 | Applied Materials, Inc. | Ionic additives for extreme low dielectric constant chemical formulations |
JP3819670B2 (ja) * | 2000-04-14 | 2006-09-13 | 富士通株式会社 | ダマシン配線を有する半導体装置 |
JP4504515B2 (ja) * | 2000-06-13 | 2010-07-14 | ルネサスエレクトロニクス株式会社 | 半導体装置及びその製造方法 |
US6989602B1 (en) * | 2000-09-21 | 2006-01-24 | Agere Systems Inc. | Dual damascene process with no passing metal features |
DE10052890B4 (de) * | 2000-10-25 | 2006-09-21 | Infineon Technologies Ag | Anordnung zur Verringerung des Widerstandes von Leiterbahnen im Layout einer integrierten Halbleiterschaltung |
US6753258B1 (en) * | 2000-11-03 | 2004-06-22 | Applied Materials Inc. | Integration scheme for dual damascene structure |
US6709945B2 (en) * | 2001-01-16 | 2004-03-23 | Micron Technology, Inc. | Reduced aspect ratio digit line contact process flow used during the formation of a semiconductor device |
KR100400033B1 (ko) * | 2001-02-08 | 2003-09-29 | 삼성전자주식회사 | 다층 배선 구조를 갖는 반도체 소자 및 그의 제조방법 |
JP2002252281A (ja) * | 2001-02-27 | 2002-09-06 | Sony Corp | 半導体装置およびその製造方法 |
US6696336B2 (en) * | 2001-05-14 | 2004-02-24 | Micron Technology, Inc. | Double sided container process used during the manufacture of a semiconductor device |
JP4587604B2 (ja) | 2001-06-13 | 2010-11-24 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US6804809B1 (en) | 2002-10-30 | 2004-10-12 | Polarfab, Llc | System and method for defining a semiconductor device layout |
US7459790B2 (en) * | 2003-10-15 | 2008-12-02 | Megica Corporation | Post passivation interconnection schemes on top of the IC chips |
US7352053B2 (en) * | 2003-10-29 | 2008-04-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Insulating layer having decreased dielectric constant and increased hardness |
DE102005045060B4 (de) * | 2005-09-21 | 2007-07-05 | Infineon Technologies Ag | Integrierte Schaltungsanordnung mit mehreren Leitstrukturlagen und Verfahren zu ihrer Herstellung |
US20070205507A1 (en) * | 2006-03-01 | 2007-09-06 | Hui-Lin Chang | Carbon and nitrogen based cap materials for metal hard mask scheme |
US8866491B2 (en) | 2011-02-24 | 2014-10-21 | Cypress Semiconductor Corporation | Tail effect correction for SLIM pattern touch panels |
US9952737B2 (en) * | 2011-02-24 | 2018-04-24 | Parade Technologies, Ltd. | Single layer touch sensor |
US9627310B2 (en) * | 2012-04-11 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with self-aligned interconnects |
KR102310122B1 (ko) | 2014-06-10 | 2021-10-08 | 삼성전자주식회사 | 논리 셀 및 이를 포함하는 집적회로 소자와 논리 셀의 제조 방법 및 집적회로 소자의 제조 방법 |
US9658726B2 (en) | 2014-07-10 | 2017-05-23 | Cypress Semiconductor Corporation | Single layer sensor pattern |
JP6741944B2 (ja) * | 2016-09-07 | 2020-08-19 | 富士通株式会社 | 電子機器及びその製造方法 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3838442A (en) * | 1970-04-15 | 1974-09-24 | Ibm | Semiconductor structure having metallization inlaid in insulating layers and method for making same |
US4576900A (en) * | 1981-10-09 | 1986-03-18 | Amdahl Corporation | Integrated circuit multilevel interconnect system and method |
JPS60102763A (ja) * | 1983-11-09 | 1985-06-06 | Hitachi Ltd | 多層厚膜混成集積回路基板 |
DE3571723D1 (en) * | 1984-08-23 | 1989-08-24 | Fairchild Semiconductor | A process for forming vias on integrated circuits |
US5084414A (en) * | 1985-03-15 | 1992-01-28 | Hewlett-Packard Company | Metal interconnection system with a planar surface |
US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
US4816895A (en) * | 1986-03-06 | 1989-03-28 | Nec Corporation | Integrated circuit device with an improved interconnection line |
US5069749A (en) * | 1986-07-29 | 1991-12-03 | Digital Equipment Corporation | Method of fabricating interconnect layers on an integrated circuit chip using seed-grown conductors |
US5063175A (en) * | 1986-09-30 | 1991-11-05 | North American Philips Corp., Signetics Division | Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material |
JPH02106968A (ja) * | 1988-10-17 | 1990-04-19 | Hitachi Ltd | 半導体集積回路装置及びその形成方法 |
US4962058A (en) * | 1989-04-14 | 1990-10-09 | International Business Machines Corporation | Process for fabricating multi-level integrated circuit wiring structure from a single metal deposit |
US5091339A (en) * | 1990-07-23 | 1992-02-25 | Microelectronics And Computer Technology Corporation | Trenching techniques for forming vias and channels in multilayer electrical interconnects |
JPH05109715A (ja) * | 1991-10-16 | 1993-04-30 | Nec Corp | 半導体装置の製造方法 |
US5612254A (en) * | 1992-06-29 | 1997-03-18 | Intel Corporation | Methods of forming an interconnect on a semiconductor substrate |
US5371047A (en) * | 1992-10-30 | 1994-12-06 | International Business Machines Corporation | Chip interconnection having a breathable etch stop layer |
US5366911A (en) * | 1994-05-11 | 1994-11-22 | United Microelectronics Corporation | VLSI process with global planarization |
US5539255A (en) * | 1995-09-07 | 1996-07-23 | International Business Machines Corporation | Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal |
-
1995
- 1995-09-21 US US08/532,915 patent/US5834845A/en not_active Expired - Lifetime
-
1996
- 1996-08-30 KR KR10-1998-0701905A patent/KR100451110B1/ko not_active IP Right Cessation
- 1996-08-30 EP EP96929801A patent/EP0852065B1/de not_active Expired - Lifetime
- 1996-08-30 WO PCT/US1996/013931 patent/WO1997011488A1/en active IP Right Grant
- 1996-08-30 DE DE69616081T patent/DE69616081T2/de not_active Expired - Lifetime
- 1996-08-30 JP JP51271497A patent/JP2001515654A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
EP0852065B1 (de) | 2001-10-17 |
US5834845A (en) | 1998-11-10 |
WO1997011488A1 (en) | 1997-03-27 |
KR100451110B1 (ko) | 2004-12-14 |
KR19990044651A (ko) | 1999-06-25 |
JP2001515654A (ja) | 2001-09-18 |
EP0852065A1 (de) | 1998-07-08 |
DE69616081T2 (de) | 2002-07-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: GLOBALFOUNDRIES INC. MAPLES CORPORATE SERVICES, KY |