DE69632817D1 - Gehäuse für mehrere halbleiterbauelemente - Google Patents

Gehäuse für mehrere halbleiterbauelemente

Info

Publication number
DE69632817D1
DE69632817D1 DE69632817T DE69632817T DE69632817D1 DE 69632817 D1 DE69632817 D1 DE 69632817D1 DE 69632817 T DE69632817 T DE 69632817T DE 69632817 T DE69632817 T DE 69632817T DE 69632817 D1 DE69632817 D1 DE 69632817D1
Authority
DE
Germany
Prior art keywords
housing
semiconductor components
several semiconductor
several
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69632817T
Other languages
English (en)
Other versions
DE69632817T2 (de
Inventor
A Kuhn
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE69632817D1 publication Critical patent/DE69632817D1/de
Application granted granted Critical
Publication of DE69632817T2 publication Critical patent/DE69632817T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49517Additional leads
    • H01L23/49531Additional leads the additional leads being a wiring board
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01RELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R33/00Coupling devices specially adapted for supporting apparatus and having one part acting as a holder providing support and electrical connection via a counterpart which is structurally associated with the apparatus, e.g. lamp holders; Separate parts thereof
    • H01R33/74Devices having four or more poles, e.g. holders for compact fluorescent lamps
    • H01R33/76Holders with sockets, clips, or analogous contacts adapted for axially-sliding engagement with parallely-arranged pins, blades, or analogous contacts on counterpart, e.g. electronic tube socket
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
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    • H01L2224/0554External layer
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01ELECTRIC ELEMENTS
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49112Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01006Carbon [C]
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    • H01L2924/01013Aluminum [Al]
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    • H01L2924/01079Gold [Au]
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    • H01L2924/013Alloys
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
DE69632817T 1995-03-13 1996-03-12 Gehäuse für mehrere halbleiterbauelemente Expired - Lifetime DE69632817T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/402,933 US5719436A (en) 1995-03-13 1995-03-13 Package housing multiple semiconductor dies
US402933 1995-03-13
PCT/US1996/003331 WO1996028860A1 (en) 1995-03-13 1996-03-12 A package housing multiple semiconductor dies

Publications (2)

Publication Number Publication Date
DE69632817D1 true DE69632817D1 (de) 2004-08-05
DE69632817T2 DE69632817T2 (de) 2005-07-14

Family

ID=23593865

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69632817T Expired - Lifetime DE69632817T2 (de) 1995-03-13 1996-03-12 Gehäuse für mehrere halbleiterbauelemente

Country Status (8)

Country Link
US (2) US5719436A (de)
EP (1) EP0815615B1 (de)
JP (1) JP3717937B2 (de)
KR (1) KR100272846B1 (de)
AU (1) AU5189596A (de)
DE (1) DE69632817T2 (de)
MY (1) MY124460A (de)
WO (1) WO1996028860A1 (de)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0137826B1 (ko) * 1994-11-15 1998-04-28 문정환 반도체 디바이스 패키지 방법 및 디바이스 패키지
US7037426B2 (en) * 2000-05-04 2006-05-02 Zenon Environmental Inc. Immersed membrane apparatus
US5677567A (en) * 1996-06-17 1997-10-14 Micron Technology, Inc. Leads between chips assembly
US6054764A (en) * 1996-12-20 2000-04-25 Texas Instruments Incorporated Integrated circuit with tightly coupled passive components
US6037661A (en) * 1996-12-20 2000-03-14 International Business Machines Multichip module
JP3545200B2 (ja) * 1997-04-17 2004-07-21 シャープ株式会社 半導体装置
JP3359846B2 (ja) * 1997-07-18 2002-12-24 シャープ株式会社 半導体装置
US5990549A (en) * 1998-02-06 1999-11-23 Intel Corporation Thermal bus bar design for an electronic cartridge
JP3077668B2 (ja) * 1998-05-01 2000-08-14 日本電気株式会社 半導体装置、半導体装置用リードフレームおよびその製造方法
GB2341482B (en) * 1998-07-30 2003-07-09 Bookham Technology Ltd Lead frame attachment for integrated optoelectronic waveguide device
SG88741A1 (en) * 1998-09-16 2002-05-21 Texas Instr Singapore Pte Ltd Multichip assembly semiconductor
US6049465A (en) * 1998-09-25 2000-04-11 Advanced Micro Devices, Inc. Signal carrying means including a carrier substrate and wire bonds for carrying signals between the cache and logic circuitry of a microprocessor
JP3886659B2 (ja) * 1999-01-13 2007-02-28 東芝マイクロエレクトロニクス株式会社 半導体装置
JP3847997B2 (ja) 1999-01-22 2006-11-22 東芝マイクロエレクトロニクス株式会社 半導体装置及び両面mcpチップ
US6890798B2 (en) 1999-06-08 2005-05-10 Intel Corporation Stacked chip packaging
US6229219B1 (en) * 2000-03-29 2001-05-08 Advanced Micro Devices, Inc. Flip chip package compatible with multiple die footprints and method of assembling the same
US6560117B2 (en) 2000-06-28 2003-05-06 Micron Technology, Inc. Packaged microelectronic die assemblies and methods of manufacture
US6552910B1 (en) 2000-06-28 2003-04-22 Micron Technology, Inc. Stacked-die assemblies with a plurality of microelectronic devices and methods of manufacture
US6525413B1 (en) 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US7298031B1 (en) 2000-08-09 2007-11-20 Micron Technology, Inc. Multiple substrate microelectronic devices and methods of manufacture
US6607937B1 (en) * 2000-08-23 2003-08-19 Micron Technology, Inc. Stacked microelectronic dies and methods for stacking microelectronic dies
US6858922B2 (en) * 2001-01-19 2005-02-22 International Rectifier Corporation Back-to-back connected power semiconductor device package
US6891257B2 (en) * 2001-03-30 2005-05-10 Fairchild Semiconductor Corporation Packaging system for die-up connection of a die-down oriented integrated circuit
US20040080056A1 (en) * 2001-03-30 2004-04-29 Lim David Chong Sook Packaging system for die-up connection of a die-down oriented integrated circuit
US6906415B2 (en) * 2002-06-27 2005-06-14 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor devices and methods
US7573136B2 (en) * 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
US7132311B2 (en) * 2002-07-26 2006-11-07 Intel Corporation Encapsulation of a stack of semiconductor dice
JP3846437B2 (ja) * 2003-03-17 2006-11-15 株式会社日立製作所 自動車用コントロールユニット
US7057116B2 (en) * 2003-06-02 2006-06-06 Intel Corporation Selective reference plane bridge(s) on folded package
TW200501358A (en) * 2003-06-20 2005-01-01 Macronix Int Co Ltd Stacking dual-chip packaging structure
US7368320B2 (en) * 2003-08-29 2008-05-06 Micron Technology, Inc. Method of fabricating a two die semiconductor assembly
US8468337B2 (en) * 2004-03-02 2013-06-18 International Business Machines Corporation Secure data transfer over a network
US7564976B2 (en) * 2004-03-02 2009-07-21 International Business Machines Corporation System and method for performing security operations on network data
US20050245062A1 (en) * 2004-04-29 2005-11-03 Jeff Kingsbury Single row bond pad arrangement
US7816182B2 (en) * 2004-11-30 2010-10-19 Stmicroelectronics Asia Pacific Pte. Ltd. Simplified multichip packaging and package design
TWI262564B (en) * 2005-04-29 2006-09-21 Holtek Semiconductor Inc Multi-functional chip construction
KR100631959B1 (ko) * 2005-09-07 2006-10-04 주식회사 하이닉스반도체 적층형 반도체 패키지 및 그 제조방법
US7816778B2 (en) * 2007-02-20 2010-10-19 Micron Technology, Inc. Packaged IC device comprising an embedded flex circuit on leadframe, and methods of making same
JP2009038142A (ja) * 2007-07-31 2009-02-19 Elpida Memory Inc 半導体積層パッケージ
JP2009295959A (ja) * 2008-05-09 2009-12-17 Panasonic Corp 半導体装置及びその製造方法
CN102906874B (zh) * 2010-05-21 2015-11-25 三菱电机株式会社 功率半导体模块
TWI406376B (zh) * 2010-06-15 2013-08-21 Powertech Technology Inc 晶片封裝構造
US8951847B2 (en) 2012-01-18 2015-02-10 Intersil Americas LLC Package leadframe for dual side assembly
US9960104B2 (en) * 2014-12-23 2018-05-01 Intel Corporation Integrated package design with wire leads for package-on-package product
US11328984B2 (en) * 2017-12-29 2022-05-10 Texas Instruments Incorporated Multi-die integrated circuit packages and methods of manufacturing the same
US11088055B2 (en) * 2018-12-14 2021-08-10 Texas Instruments Incorporated Package with dies mounted on opposing surfaces of a leadframe

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63107149A (ja) * 1986-10-24 1988-05-12 Hitachi Ltd マルチチツプモジユ−ル
JPS63244654A (ja) * 1987-03-31 1988-10-12 Toshiba Corp 樹脂封止型集積回路装置
FR2619959B1 (fr) * 1987-08-31 1991-06-14 Thomson Semiconducteurs Circuit de detection de lumiere
JP2522524B2 (ja) * 1988-08-06 1996-08-07 株式会社東芝 半導体装置の製造方法
JPH02105446A (ja) * 1988-10-13 1990-04-18 Nec Corp 混成集積回路
JPH02201948A (ja) * 1989-01-30 1990-08-10 Toshiba Corp 半導体装置パッケージ
JPH03105952A (ja) * 1989-09-19 1991-05-02 Nec Kyushu Ltd 表面実装型半導体装置
US5012323A (en) * 1989-11-20 1991-04-30 Micron Technology, Inc. Double-die semiconductor package having a back-bonded die and a face-bonded die interconnected on a single leadframe
US5019893A (en) * 1990-03-01 1991-05-28 Motorola, Inc. Single package, multiple, electrically isolated power semiconductor devices
JPH0439955A (ja) * 1990-06-05 1992-02-10 Mitsubishi Electric Corp 半導体装置
JPH0449650A (ja) * 1990-06-19 1992-02-19 Oki Electric Ind Co Ltd モールドパッケージ型ハイブリッドic
US5053992A (en) * 1990-10-04 1991-10-01 General Instrument Corporation Prevention of inspection of secret data stored in encapsulated integrated circuit chip
JP2593956B2 (ja) * 1990-10-18 1997-03-26 シャープ株式会社 絶縁ゲート型電界効果トランジスタの高しきい値電圧化方法
JPH04155856A (ja) * 1990-10-18 1992-05-28 Hitachi Ltd 混成集積回路装置およびその製造方法
JPH0536893A (ja) * 1991-08-02 1993-02-12 Nec Corp 混成集積回路
JPH05136303A (ja) * 1991-11-08 1993-06-01 Nec Corp 電子デバイス用ヒートシンク
JP2843464B2 (ja) * 1992-09-01 1999-01-06 シャープ株式会社 固体撮像装置
US5615475A (en) * 1995-01-30 1997-04-01 Staktek Corporation Method of manufacturing an integrated package having a pair of die on a common lead frame

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AU5189596A (en) 1996-10-02
US5793101A (en) 1998-08-11
EP0815615A1 (de) 1998-01-07
JP3717937B2 (ja) 2005-11-16
EP0815615B1 (de) 2004-06-30
KR19980702651A (ko) 1998-08-05
MY124460A (en) 2006-06-30
JPH11502063A (ja) 1999-02-16
EP0815615A4 (de) 2000-12-06
US5719436A (en) 1998-02-17
DE69632817T2 (de) 2005-07-14
KR100272846B1 (ko) 2000-11-15
WO1996028860A1 (en) 1996-09-19

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