DE69226098D1 - Lokale Kontaktverbindungen für integrierte Schaltungen - Google Patents

Lokale Kontaktverbindungen für integrierte Schaltungen

Info

Publication number
DE69226098D1
DE69226098D1 DE69226098T DE69226098T DE69226098D1 DE 69226098 D1 DE69226098 D1 DE 69226098D1 DE 69226098 T DE69226098 T DE 69226098T DE 69226098 T DE69226098 T DE 69226098T DE 69226098 D1 DE69226098 D1 DE 69226098D1
Authority
DE
Germany
Prior art keywords
integrated circuits
local contact
contact connections
connections
local
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69226098T
Other languages
English (en)
Other versions
DE69226098T2 (de
Inventor
Che-Chia Wei
Fu-Tai Liou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Application granted granted Critical
Publication of DE69226098D1 publication Critical patent/DE69226098D1/de
Publication of DE69226098T2 publication Critical patent/DE69226098T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69226098T 1991-01-31 1992-01-30 Lokale Kontaktverbindungen für integrierte Schaltungen Expired - Fee Related DE69226098T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/648,554 US5124280A (en) 1991-01-31 1991-01-31 Local interconnect for integrated circuits

Publications (2)

Publication Number Publication Date
DE69226098D1 true DE69226098D1 (de) 1998-08-13
DE69226098T2 DE69226098T2 (de) 1998-10-29

Family

ID=24601268

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69226098T Expired - Fee Related DE69226098T2 (de) 1991-01-31 1992-01-30 Lokale Kontaktverbindungen für integrierte Schaltungen

Country Status (5)

Country Link
US (2) US5124280A (de)
EP (1) EP0497595B1 (de)
JP (1) JPH04335525A (de)
KR (1) KR920015465A (de)
DE (1) DE69226098T2 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5418179A (en) * 1988-05-31 1995-05-23 Yamaha Corporation Process of fabricating complementary inverter circuit having multi-level interconnection
JPH0758701B2 (ja) * 1989-06-08 1995-06-21 株式会社東芝 半導体装置の製造方法
JPH03141645A (ja) * 1989-07-10 1991-06-17 Texas Instr Inc <Ti> ポリサイドによる局所的相互接続方法とその方法により製造された半導体素子
US5266509A (en) * 1990-05-11 1993-11-30 North American Philips Corporation Fabrication method for a floating-gate field-effect transistor structure
JP2757927B2 (ja) * 1990-06-28 1998-05-25 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体基板上の隔置されたシリコン領域の相互接続方法
JPH04242938A (ja) * 1991-01-08 1992-08-31 Mitsubishi Electric Corp 半導体装置およびその製造方法
DE69226987T2 (de) * 1991-05-03 1999-02-18 Sgs-Thomson Microelectronics, Inc., Carrollton, Tex. Lokalverbindungen für integrierte Schaltungen
US5227333A (en) * 1992-02-27 1993-07-13 International Business Machines Corporation Local interconnection having a germanium layer
US5175127A (en) * 1992-06-02 1992-12-29 Micron Technology, Inc. Self-aligned interlayer contact process using a plasma etch of photoresist
US5229326A (en) * 1992-06-23 1993-07-20 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
USRE40790E1 (en) 1992-06-23 2009-06-23 Micron Technology, Inc. Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device
JPH06188385A (ja) * 1992-10-22 1994-07-08 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3067433B2 (ja) * 1992-12-04 2000-07-17 キヤノン株式会社 半導体装置の製造方法
TW230266B (de) * 1993-01-26 1994-09-11 American Telephone & Telegraph
JP2591446B2 (ja) * 1993-10-18 1997-03-19 日本電気株式会社 半導体装置およびその製造方法
DE4339919C2 (de) * 1993-11-23 1999-03-04 Siemens Ag Herstellverfahren für eine aus Silizid bestehende Anschlußfläche für ein Siliziumgebiet
JPH07221174A (ja) * 1993-12-10 1995-08-18 Canon Inc 半導体装置及びその製造方法
US5521118A (en) * 1994-12-22 1996-05-28 International Business Machines Corporation Sidewall strap
JPH08181205A (ja) * 1994-12-26 1996-07-12 Mitsubishi Electric Corp 半導体装置の配線構造およびその製造方法
US5858875A (en) * 1995-02-03 1999-01-12 National Semiconductor Corporation Integrated circuits with borderless vias
US5757077A (en) * 1995-02-03 1998-05-26 National Semiconductor Corporation Integrated circuits with borderless vias
US5656543A (en) * 1995-02-03 1997-08-12 National Semiconductor Corporation Fabrication of integrated circuits with borderless vias
US5536683A (en) * 1995-06-15 1996-07-16 United Microelectronics Corporation Method for interconnecting semiconductor devices
KR100206878B1 (ko) * 1995-12-29 1999-07-01 구본준 반도체소자 제조방법
US5952720A (en) * 1996-05-06 1999-09-14 United Microelectronics Corp. Buried contact structure
US5869391A (en) * 1996-08-20 1999-02-09 Micron Technology, Inc. Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry
US5827762A (en) * 1997-05-02 1998-10-27 National Semiconductor Corporation Method for forming buried interconnect structue having stability at high temperatures
US6207543B1 (en) 1997-06-30 2001-03-27 Vlsi Technology, Inc. Metallization technique for gate electrodes and local interconnects
US6420273B1 (en) 1997-06-30 2002-07-16 Koninklijke Philips Electronics N.V. Self-aligned etch-stop layer formation for semiconductor devices
US6403458B2 (en) 1998-04-03 2002-06-11 Micron Technology, Inc. Method for fabricating local interconnect structure for integrated circuit devices, source structures
US6576544B1 (en) * 2001-09-28 2003-06-10 Lsi Logic Corporation Local interconnect
US6559043B1 (en) * 2002-01-11 2003-05-06 Taiwan Semiconductor Manufacturing Company Method for electrical interconnection employing salicide bridge
US7317217B2 (en) * 2004-09-17 2008-01-08 International Business Machines Corporation Semiconductor scheme for reduced circuit area in a simplified process
US7790611B2 (en) * 2007-05-17 2010-09-07 International Business Machines Corporation Method for FEOL and BEOL wiring
FR2976725B1 (fr) * 2011-06-15 2013-06-28 St Microelectronics Sa Dispositif semiconducteur bidirectionnel declenchable utilisable sur silicium sur isolant
FR2987172A1 (fr) 2012-02-17 2013-08-23 St Microelectronics Sa Dispositif semiconducteur bidirectionnel de protection contre les decharges electrostatiques, utilisable sur silicium sur isolant
US8809184B2 (en) 2012-05-07 2014-08-19 Globalfoundries Inc. Methods of forming contacts for semiconductor devices using a local interconnect processing scheme

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4476482A (en) * 1981-05-29 1984-10-09 Texas Instruments Incorporated Silicide contacts for CMOS devices
JPH0618213B2 (ja) * 1982-06-25 1994-03-09 松下電子工業株式会社 半導体装置の製造方法
JPS60134466A (ja) * 1983-12-23 1985-07-17 Hitachi Ltd 半導体装置およびその製造方法
US4581815A (en) * 1984-03-01 1986-04-15 Advanced Micro Devices, Inc. Integrated circuit structure having intermediate metal silicide layer and method of making same
US4975756A (en) * 1985-05-01 1990-12-04 Texas Instruments Incorporated SRAM with local interconnect
JPS62204523A (ja) * 1986-03-04 1987-09-09 Nec Corp コンタクト電極の形成方法
JPH02504448A (ja) * 1988-05-24 1990-12-13 マイクロン・テクノロジー・インコーポレイテッド ＴｉＳｉ２ローカル・インターコネクト
US5053349A (en) * 1988-06-16 1991-10-01 Kabushiki Kaisha Toshiba Method for interconnecting semiconductor devices
DE3828999C2 (de) * 1988-08-26 1996-01-18 Hella Kg Hueck & Co Scheibenwaschanlage für Kraftfahrzeuge, insbesondere Streuscheibenwaschanlage

Also Published As

Publication number Publication date
EP0497595A3 (en) 1992-09-30
DE69226098T2 (de) 1998-10-29
US5349229A (en) 1994-09-20
EP0497595B1 (de) 1998-07-08
KR920015465A (ko) 1992-08-26
EP0497595A2 (de) 1992-08-05
US5124280A (en) 1992-06-23
JPH04335525A (ja) 1992-11-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee