DE69226987D1 - Lokalverbindungen für integrierte Schaltungen - Google Patents

Lokalverbindungen für integrierte Schaltungen

Info

Publication number
DE69226987D1
DE69226987D1 DE69226987T DE69226987T DE69226987D1 DE 69226987 D1 DE69226987 D1 DE 69226987D1 DE 69226987 T DE69226987 T DE 69226987T DE 69226987 T DE69226987 T DE 69226987T DE 69226987 D1 DE69226987 D1 DE 69226987D1
Authority
DE
Germany
Prior art keywords
integrated circuits
local connections
connections
local
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69226987T
Other languages
English (en)
Other versions
DE69226987T2 (de
Inventor
Fusen Chen
Fu-Tai Liou
Girish Dixit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69226987D1 publication Critical patent/DE69226987D1/de
Application granted granted Critical
Publication of DE69226987T2 publication Critical patent/DE69226987T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/019—Contacts of silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/915—Active solid-state devices, e.g. transistors, solid-state diodes with titanium nitride portion or region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE69226987T 1991-05-03 1992-05-01 Lokalverbindungen für integrierte Schaltungen Expired - Fee Related DE69226987T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US69558391A 1991-05-03 1991-05-03

Publications (2)

Publication Number Publication Date
DE69226987D1 true DE69226987D1 (de) 1998-10-22
DE69226987T2 DE69226987T2 (de) 1999-02-18

Family

ID=24793607

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69226987T Expired - Fee Related DE69226987T2 (de) 1991-05-03 1992-05-01 Lokalverbindungen für integrierte Schaltungen

Country Status (4)

Country Link
US (2) US5319245A (de)
EP (1) EP0517368B1 (de)
JP (1) JPH05152246A (de)
DE (1) DE69226987T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69430461T2 (de) * 1993-01-12 2002-11-14 Texas Instruments Inc., Dallas Neue Verbindungstechnik in bedeckten TiSi2/TiN
JP3256048B2 (ja) * 1993-09-20 2002-02-12 富士通株式会社 半導体装置及びその製造方法
JP3396286B2 (ja) * 1994-02-28 2003-04-14 三菱電機株式会社 半導体集積回路装置およびその製造方法
JPH07263544A (ja) * 1994-03-17 1995-10-13 Fujitsu Ltd 半導体装置及びその製造方法
US5923999A (en) * 1996-10-29 1999-07-13 International Business Machines Corporation Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device
KR100240615B1 (ko) * 1997-03-13 2000-01-15 김영환 반도체장치의제조방법
JP3567081B2 (ja) * 1997-05-30 2004-09-15 ルーセント テクノロジーズ インコーポレーテッド Ｓｒａｍデバイスおよびその製造方法
US5807779A (en) * 1997-07-30 1998-09-15 Taiwan Semiconductor Manufacturing Company Ltd. Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact process
US6060328A (en) * 1997-09-05 2000-05-09 Advanced Micro Devices, Inc. Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process
US5920796A (en) * 1997-09-05 1999-07-06 Advanced Micro Devices, Inc. In-situ etch of BARC layer during formation of local interconnects
US6060404A (en) * 1997-09-05 2000-05-09 Advanced Micro Devices, Inc. In-situ deposition of stop layer and dielectric layer during formation of local interconnects
US6114235A (en) * 1997-09-05 2000-09-05 Advanced Micro Devices, Inc. Multipurpose cap layer dielectric
US6153933A (en) * 1997-09-05 2000-11-28 Advanced Micro Devices, Inc. Elimination of residual materials in a multiple-layer interconnect structure
US6048791A (en) * 1998-03-31 2000-04-11 Kabushiki Kaisha Toshiba Semiconductor device with electrode formed of conductive layer consisting of polysilicon layer and metal-silicide layer and its manufacturing method
US6403458B2 (en) * 1998-04-03 2002-06-11 Micron Technology, Inc. Method for fabricating local interconnect structure for integrated circuit devices, source structures
US6100185A (en) * 1998-08-14 2000-08-08 Micron Technology, Inc. Semiconductor processing method of forming a high purity <200> grain orientation tin layer and semiconductor processing method of forming a conductive interconnect line
JP2000200838A (ja) * 1998-10-30 2000-07-18 Seiko Epson Corp 半導体記憶装置およびその製造方法
US6365507B1 (en) 1999-03-01 2002-04-02 Micron Technology, Inc. Method of forming integrated circuitry
US6524951B2 (en) * 1999-03-01 2003-02-25 Micron Technology, Inc. Method of forming a silicide interconnect over a silicon comprising substrate and method of forming a stack of refractory metal nitride over refractory metal silicide over silicon
US6372668B2 (en) 2000-01-18 2002-04-16 Advanced Micro Devices, Inc. Method of forming silicon oxynitride films
DE60129538T2 (de) 2000-03-14 2008-04-10 James Hardie International Finance B.V. Faserzementbaumaterialien mit zusatzstoffen niedriger dichte
US6812529B2 (en) * 2001-03-15 2004-11-02 Micron Technology, Inc. Suppression of cross diffusion and gate depletion
US6576544B1 (en) * 2001-09-28 2003-06-10 Lsi Logic Corporation Local interconnect
DE10219361B4 (de) * 2002-04-30 2008-04-30 Advanced Micro Devices, Inc., Sunnyvale Ein Halbleiterelement mit einer verbesserten lokalen Verbindungsstruktur und ein Verfahren zur Herstellung eines derartigen Elements
US7993570B2 (en) 2002-10-07 2011-08-09 James Hardie Technology Limited Durable medium-density fibre cement composite
US7998571B2 (en) 2004-07-09 2011-08-16 James Hardie Technology Limited Composite cement article incorporating a powder coating and methods of making same
AU2007236561B2 (en) 2006-04-12 2012-12-20 James Hardie Technology Limited A surface sealed reinforced building element
US8209927B2 (en) 2007-12-20 2012-07-03 James Hardie Technology Limited Structural fiber cement building materials

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3132809A1 (de) * 1981-08-19 1983-03-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-feldeffekttransistoren, insbesondere von komplementaeren mos-feldeffekttransistorenschaltungen mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene
JPH0666427B2 (ja) * 1983-09-16 1994-08-24 セイコーエプソン株式会社 Ｍｏｓ型半導体集積回路装置の製造方法
US4829363A (en) * 1984-04-13 1989-05-09 Fairchild Camera And Instrument Corp. Structure for inhibiting dopant out-diffusion
US4640004A (en) * 1984-04-13 1987-02-03 Fairchild Camera & Instrument Corp. Method and structure for inhibiting dopant out-diffusion
US4677735A (en) * 1984-05-24 1987-07-07 Texas Instruments Incorporated Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer
US4873204A (en) * 1984-06-15 1989-10-10 Hewlett-Packard Company Method for making silicide interconnection structures for integrated circuit devices
US4920071A (en) * 1985-03-15 1990-04-24 Fairchild Camera And Instrument Corporation High temperature interconnect system for an integrated circuit
US4933742A (en) * 1985-03-22 1990-06-12 General Electric Company Metallization contact system for large scale integrated circuits
US4676866A (en) * 1985-05-01 1987-06-30 Texas Instruments Incorporated Process to increase tin thickness
US4804636A (en) * 1985-05-01 1989-02-14 Texas Instruments Incorporated Process for making integrated circuits having titanium nitride triple interconnect
DE3650170T2 (de) * 1985-05-13 1995-05-18 Toshiba Kawasaki Kk Halbleiteranordnung mit Verbindungselektroden.
US4746219A (en) * 1986-03-07 1988-05-24 Texas Instruments Incorporated Local interconnect
US4784973A (en) * 1987-08-24 1988-11-15 Inmos Corporation Semiconductor contact silicide/nitride process with control for silicide thickness
EP0704883A3 (de) * 1988-02-11 1997-07-09 Sgs Thomson Microelectronics Schwerschmelzende Metallsilicid-Verkapselung zum Schutz mehrlagiger Policide
US4962414A (en) * 1988-02-11 1990-10-09 Sgs-Thomson Microelectronics, Inc. Method for forming a contact VIA
US5162262A (en) * 1989-03-14 1992-11-10 Mitsubishi Denki Kabushiki Kaisha Multi-layered interconnection structure for a semiconductor device and manufactured method thereof
JP2537413B2 (ja) * 1989-03-14 1996-09-25 三菱電機株式会社 半導体装置およびその製造方法
US4920073A (en) * 1989-05-11 1990-04-24 Texas Instruments, Incorporated Selective silicidation process using a titanium nitride protective layer
US4978637A (en) * 1989-05-31 1990-12-18 Sgs-Thomson Microelectronics, Inc. Local interconnect process for integrated circuits
FR2658951B1 (fr) * 1990-02-23 1992-05-07 Bonis Maurice Procede de fabrication d'un circuit integre pour filiere analogique rapide utilisant des lignes d'interconnexions locales en siliciure.
US5094981A (en) * 1990-04-17 1992-03-10 North American Philips Corporation, Signetics Div. Technique for manufacturing interconnections for a semiconductor device by annealing layers of titanium and a barrier material above 550° C.
US5124280A (en) * 1991-01-31 1992-06-23 Sgs-Thomson Microelectronics, Inc. Local interconnect for integrated circuits
US5190893A (en) * 1991-04-01 1993-03-02 Motorola Inc. Process for fabricating a local interconnect structure in a semiconductor device
JPH05243178A (ja) * 1991-10-03 1993-09-21 Hewlett Packard Co <Hp> 半導体集積回路用相互接続体形成方法

Also Published As

Publication number Publication date
EP0517368A3 (en) 1993-06-02
EP0517368A2 (de) 1992-12-09
US5319245A (en) 1994-06-07
DE69226987T2 (de) 1999-02-18
JPH05152246A (ja) 1993-06-18
EP0517368B1 (de) 1998-09-16
US5391520A (en) 1995-02-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee