DE3774062D1 - Verbindungsleitungen fuer integrierte schaltungen. - Google Patents

Verbindungsleitungen fuer integrierte schaltungen.

Info

Publication number
DE3774062D1
DE3774062D1 DE8787307269T DE3774062T DE3774062D1 DE 3774062 D1 DE3774062 D1 DE 3774062D1 DE 8787307269 T DE8787307269 T DE 8787307269T DE 3774062 T DE3774062 T DE 3774062T DE 3774062 D1 DE3774062 D1 DE 3774062D1
Authority
DE
Germany
Prior art keywords
integrated circuits
connection lines
lines
connection
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787307269T
Other languages
English (en)
Inventor
Joseph Lebowitz
William Thomas Lynch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Application granted granted Critical
Publication of DE3774062D1 publication Critical patent/DE3774062D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8787307269T 1986-08-25 1987-08-18 Verbindungsleitungen fuer integrierte schaltungen. Expired - Lifetime DE3774062D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US89998286A 1986-08-25 1986-08-25

Publications (1)

Publication Number Publication Date
DE3774062D1 true DE3774062D1 (de) 1991-11-28

Family

ID=25411816

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787307269T Expired - Lifetime DE3774062D1 (de) 1986-08-25 1987-08-18 Verbindungsleitungen fuer integrierte schaltungen.

Country Status (8)

Country Link
US (1) US4914502A (de)
EP (1) EP0262780B1 (de)
JP (1) JPH0732195B2 (de)
KR (1) KR900008181B1 (de)
CA (1) CA1305255C (de)
DE (1) DE3774062D1 (de)
HK (1) HK96093A (de)
SG (1) SG123792G (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2650377B2 (ja) * 1988-12-13 1997-09-03 富士通株式会社 半導体集積回路
ATE171307T1 (de) * 1989-05-22 1998-10-15 Advanced Micro Devices Inc Leiterstruktur für eine integrierte schaltung
JP2953708B2 (ja) * 1989-07-31 1999-09-27 株式会社東芝 ダイナミック型半導体記憶装置
JPH03171662A (ja) * 1989-11-29 1991-07-25 Sharp Corp 信号線システム
KR920010344B1 (ko) * 1989-12-29 1992-11-27 삼성전자주식회사 반도체 메모리 어레이의 구성방법
KR930001737B1 (ko) * 1989-12-29 1993-03-12 삼성전자 주식회사 반도체 메모리 어레이의 워드라인 배열방법
JP2884962B2 (ja) * 1992-10-30 1999-04-19 日本電気株式会社 半導体メモリ
US5864181A (en) 1993-09-15 1999-01-26 Micron Technology, Inc. Bi-level digit line architecture for high density DRAMs
JP2638487B2 (ja) * 1994-06-30 1997-08-06 日本電気株式会社 半導体記憶装置
EP0697735B1 (de) * 1994-08-15 2002-03-27 International Business Machines Corporation Anordnung mit einem einzigen Verdrillungsgebiet und Verfahren für gepaarte linienförmige Leiter in integrierten Schaltungen
US6043562A (en) * 1996-01-26 2000-03-28 Micron Technology, Inc. Digit line architecture for dynamic memory
US5949698A (en) 1998-02-20 1999-09-07 Micron Technology, Inc. Twisted global column decoder
US7259464B1 (en) * 2000-05-09 2007-08-21 Micron Technology, Inc. Vertical twist scheme for high-density DRAMs
US6947324B1 (en) 2000-06-28 2005-09-20 Marvell International Ltd. Logic process DRAM
US7184290B1 (en) 2000-06-28 2007-02-27 Marvell International Ltd. Logic process DRAM
US6570781B1 (en) 2000-06-28 2003-05-27 Marvell International Ltd. Logic process DRAM
US6259621B1 (en) * 2000-07-06 2001-07-10 Micron Technology, Inc. Method and apparatus for minimization of data line coupling in a semiconductor memory device
DE10034083C1 (de) * 2000-07-13 2002-03-14 Infineon Technologies Ag Halbleiterspeicher mit wahlfreiem Zugeriff mit reduziertem Signalüberkoppeln
US7012826B2 (en) * 2004-03-31 2006-03-14 International Business Machines Corporation Bitline twisting structure for memory arrays incorporating reference wordlines
US7244995B2 (en) * 2004-10-18 2007-07-17 Texas Instruments Incorporated Scrambling method to reduce wordline coupling noise
US7830221B2 (en) * 2008-01-25 2010-11-09 Micron Technology, Inc. Coupling cancellation scheme

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092734A (en) * 1971-12-14 1978-05-30 Texas Instruments Incorporated Analogue memory
US3757028A (en) * 1972-09-18 1973-09-04 J Schlessel Terference printed board and similar transmission line structure for reducing in
US3946421A (en) * 1974-06-28 1976-03-23 Texas Instruments Incorporated Multi phase double level metal charge coupled device
US4206370A (en) * 1976-12-20 1980-06-03 Motorola, Inc. Serial-parallel-loop CCD register
US4238694A (en) * 1977-05-23 1980-12-09 Bell Telephone Laboratories, Incorporated Healing radiation defects in semiconductors
US4591891A (en) * 1978-06-05 1986-05-27 Texas Instruments Incorporated Post-metal electron beam programmable MOS read only memory
US4251876A (en) * 1978-11-03 1981-02-17 Mostek Corporation Extremely low current load device for integrated circuit
US4242700A (en) * 1979-01-22 1980-12-30 Rca Corporation Line transfer CCD imagers
US4589008A (en) * 1980-01-28 1986-05-13 Rca Corporation Apparatus for electrically joining the ends of substantially parallel semiconductor lines
US4402063A (en) * 1981-09-28 1983-08-30 Bell Telephone Laboratories, Incorporated Flip-flop detector array for minimum geometry semiconductor memory apparatus
JPS58111183A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd ダイナミツクｒａｍ集積回路装置
JPS59231852A (ja) * 1983-06-15 1984-12-26 Hitachi Ltd 半導体装置
JPS60254635A (ja) * 1984-05-30 1985-12-16 Fujitsu Ltd 集積回路装置
US4651183A (en) * 1984-06-28 1987-03-17 International Business Machines Corporation High density one device memory cell arrays

Also Published As

Publication number Publication date
KR900008181B1 (ko) 1990-11-05
JPS6356938A (ja) 1988-03-11
EP0262780A1 (de) 1988-04-06
CA1305255C (en) 1992-07-14
US4914502A (en) 1990-04-03
JPH0732195B2 (ja) 1995-04-10
EP0262780B1 (de) 1991-10-23
SG123792G (en) 1993-02-19
HK96093A (en) 1993-09-24
KR880003415A (ko) 1988-05-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN