KR880003415A - 반도체 집적 회로 - Google Patents

반도체 집적 회로 Download PDF

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Publication number
KR880003415A
KR880003415A KR870009198A KR870009198A KR880003415A KR 880003415 A KR880003415 A KR 880003415A KR 870009198 A KR870009198 A KR 870009198A KR 870009198 A KR870009198 A KR 870009198A KR 880003415 A KR880003415 A KR 880003415A
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KR
South Korea
Prior art keywords
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integrated circuit
semiconductor integrated
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advanced
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Application number
KR870009198A
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English (en)
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KR900008181B1 (ko
Inventor
레보위츠 죠셉
토마스 린치 윌리암
Original Assignee
오레그 이· 앨버
아메리칸 텔리폰 앤드 텔레그라프 캄파니
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 오레그 이· 앨버, 아메리칸 텔리폰 앤드 텔레그라프 캄파니 filed Critical 오레그 이· 앨버
Publication of KR880003415A publication Critical patent/KR880003415A/ko
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Publication of KR900008181B1 publication Critical patent/KR900008181B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 집적 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예에 따르는 상호접속 라인 전진 배열 예시부분의 물리적 배치를 도시하는 스틱다이아그램.
제2도는 또다른 실시예에 따르는 상호접속 라인 전진 배열 예시부분의 물리적 배치를 도시하는 스틱 다이아그램.
* 도면의 주요부분에 대한 부호의 설명
1, 2,…12 : 라인.

Claims (3)

  1. 도통하는 라인 배열을 포함하는 반도체 집적 회로에 있어서, 각각의 라인(1)은 각각의 라인을 따라 여러 위치에서 다른 라인(2, 6, 10…)중 다른 하나의 한 측부상에 위치된 이웃하는 라인을 갖는 것을 특징으로하는 반도체 집적 회로.
  2. 제1항에 있어서, 각각의 라인은 각각의 라인을 따라 여러 위치에서 다른 라인중 다른 하나의 다른 측 부상에 위치된 이웃하는 라인을 갖는 것을 특징으로 하는 반도체 집적 회로.
  3. 제2항에 있어서, 배열의 한 위치에서 짝수-번호 라인은 라인방향을 횡단하는 제1방향으로 전진하며 홀수-번호 라인은 라인방향을 횡단하는 제2방향으로 전진하며, 제2방향은 제1방향과 반대인 것을 특징으로 하는 반도체 집적 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870009198A 1986-08-25 1987-08-22 반도체 집적 회로 KR900008181B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US89998286A 1986-08-25 1986-08-25
US899,982 1986-08-25
US899982 1986-08-25

Publications (2)

Publication Number Publication Date
KR880003415A true KR880003415A (ko) 1988-05-17
KR900008181B1 KR900008181B1 (ko) 1990-11-05

Family

ID=25411816

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870009198A KR900008181B1 (ko) 1986-08-25 1987-08-22 반도체 집적 회로

Country Status (8)

Country Link
US (1) US4914502A (ko)
EP (1) EP0262780B1 (ko)
JP (1) JPH0732195B2 (ko)
KR (1) KR900008181B1 (ko)
CA (1) CA1305255C (ko)
DE (1) DE3774062D1 (ko)
HK (1) HK96093A (ko)
SG (1) SG123792G (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2650377B2 (ja) * 1988-12-13 1997-09-03 富士通株式会社 半導体集積回路
ATE171307T1 (de) * 1989-05-22 1998-10-15 Advanced Micro Devices Inc Leiterstruktur für eine integrierte schaltung
JP2953708B2 (ja) * 1989-07-31 1999-09-27 株式会社東芝 ダイナミック型半導体記憶装置
JPH03171662A (ja) * 1989-11-29 1991-07-25 Sharp Corp 信号線システム
KR920010344B1 (ko) * 1989-12-29 1992-11-27 삼성전자주식회사 반도체 메모리 어레이의 구성방법
KR930001737B1 (ko) * 1989-12-29 1993-03-12 삼성전자 주식회사 반도체 메모리 어레이의 워드라인 배열방법
JP2884962B2 (ja) * 1992-10-30 1999-04-19 日本電気株式会社 半導体メモリ
US5864181A (en) 1993-09-15 1999-01-26 Micron Technology, Inc. Bi-level digit line architecture for high density DRAMs
JP2638487B2 (ja) * 1994-06-30 1997-08-06 日本電気株式会社 半導体記憶装置
DE69526006T2 (de) * 1994-08-15 2003-01-02 Ibm Anordnung mit einem einzigen Verdrillungsgebiet und Verfahren für gepaarte linienförmige Leiter in integrierten Schaltungen
US6043562A (en) 1996-01-26 2000-03-28 Micron Technology, Inc. Digit line architecture for dynamic memory
US5949698A (en) * 1998-02-20 1999-09-07 Micron Technology, Inc. Twisted global column decoder
US7259464B1 (en) * 2000-05-09 2007-08-21 Micron Technology, Inc. Vertical twist scheme for high-density DRAMs
US7184290B1 (en) 2000-06-28 2007-02-27 Marvell International Ltd. Logic process DRAM
US6947324B1 (en) 2000-06-28 2005-09-20 Marvell International Ltd. Logic process DRAM
US6570781B1 (en) 2000-06-28 2003-05-27 Marvell International Ltd. Logic process DRAM
US6259621B1 (en) * 2000-07-06 2001-07-10 Micron Technology, Inc. Method and apparatus for minimization of data line coupling in a semiconductor memory device
DE10034083C1 (de) * 2000-07-13 2002-03-14 Infineon Technologies Ag Halbleiterspeicher mit wahlfreiem Zugeriff mit reduziertem Signalüberkoppeln
US7012826B2 (en) * 2004-03-31 2006-03-14 International Business Machines Corporation Bitline twisting structure for memory arrays incorporating reference wordlines
US7244995B2 (en) * 2004-10-18 2007-07-17 Texas Instruments Incorporated Scrambling method to reduce wordline coupling noise
US7830221B2 (en) * 2008-01-25 2010-11-09 Micron Technology, Inc. Coupling cancellation scheme

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4092734A (en) * 1971-12-14 1978-05-30 Texas Instruments Incorporated Analogue memory
US3757028A (en) * 1972-09-18 1973-09-04 J Schlessel Terference printed board and similar transmission line structure for reducing in
US3946421A (en) * 1974-06-28 1976-03-23 Texas Instruments Incorporated Multi phase double level metal charge coupled device
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JPS58111183A (ja) * 1981-12-25 1983-07-02 Hitachi Ltd ダイナミツクｒａｍ集積回路装置
JPS59231852A (ja) * 1983-06-15 1984-12-26 Hitachi Ltd 半導体装置
JPS60254635A (ja) * 1984-05-30 1985-12-16 Fujitsu Ltd 集積回路装置
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Also Published As

Publication number Publication date
HK96093A (en) 1993-09-24
US4914502A (en) 1990-04-03
SG123792G (en) 1993-02-19
JPS6356938A (ja) 1988-03-11
EP0262780B1 (en) 1991-10-23
EP0262780A1 (en) 1988-04-06
DE3774062D1 (de) 1991-11-28
CA1305255C (en) 1992-07-14
KR900008181B1 (ko) 1990-11-05
JPH0732195B2 (ja) 1995-04-10

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