KR920020515A - 반도체 판독전용메모리 - Google Patents

반도체 판독전용메모리 Download PDF

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Publication number
KR920020515A
KR920020515A KR1019920005912A KR920005912A KR920020515A KR 920020515 A KR920020515 A KR 920020515A KR 1019920005912 A KR1019920005912 A KR 1019920005912A KR 920005912 A KR920005912 A KR 920005912A KR 920020515 A KR920020515 A KR 920020515A
Authority
KR
South Korea
Prior art keywords
bit line
memory
semiconductor read
bit
bit lines
Prior art date
Application number
KR1019920005912A
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English (en)
Other versions
KR950010300B1 (ko
Inventor
야수히로 홋타
Original Assignee
쓰지 하루오
샤프 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 쓰지 하루오, 샤프 가부시끼가이샤 filed Critical 쓰지 하루오
Publication of KR920020515A publication Critical patent/KR920020515A/ko
Application granted granted Critical
Publication of KR950010300B1 publication Critical patent/KR950010300B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • G11C17/126—Virtual ground arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 판독전용메모리
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일 실시예의 ROM 일부를 나타내는 회로도,
제2도는 디퓨젼(diffusion)비트라인을 가지는 실시예의 레이아웃.

Claims (4)

  1. 병렬로 배열되는 복수의 제1비트라인; 각 그룹에 있어 메모리셀이 두 개의 인접한 상기 제1비트라인사이에 병렬로 접속되는 복수의 메모리셀 그룹; 상기 제1비트라인에 대한 제2비트라인의 비율이 1:2가 되고 상기 제1비트라인에 병렬로 배열되는 제2비트라인; 각각이 홀수의 상기 제1비트라인의 일단과 홀수의 상기 제2비트라인의 일단사이에 접속되는 제1뱅크선택스위치 그룹; 그리고 각각이 짝수의 상기 제1비트라인의 일단과 짝수의 상기 제2비트라인의 일단사이에 접속되는 제2뱅크선택 스위치 그룹을 구성하는 반도체 판독전용 메모리.
  2. 제1항에 있어서, 상기 제1 및 제2뱅크선택 스위치가 복수의 두 개의 인접한 선택스위치쌍을 이용하여 구성되고, 상기 인접한 두 개의 선택스위치가 상기 제2비트 라인의 동일한 것에 접속되는 반도체 판독전용 메모리.
  3. 제1항에 있어서, 상기 메모리셀과 상기 선택스위치가 MOSFETs인 반도체 판독전용 메모리.
  4. 제1항에 있어서, 상기 제1비트라인이 디퓨젼층에 의해 이루어지고, 상기 제2비트라인이 메탈라인인 반도체 판독전용 메모리.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920005912A 1991-04-10 1992-04-09 반도체 판독전용 메모리 KR950010300B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP91-077914 1991-04-10
JP91-77914 1991-04-10
JP3077914A JPH04311900A (ja) 1991-04-10 1991-04-10 半導体読み出し専用メモリ

Publications (2)

Publication Number Publication Date
KR920020515A true KR920020515A (ko) 1992-11-21
KR950010300B1 KR950010300B1 (ko) 1995-09-14

Family

ID=13647345

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920005912A KR950010300B1 (ko) 1991-04-10 1992-04-09 반도체 판독전용 메모리

Country Status (6)

Country Link
US (1) US5268861A (ko)
EP (1) EP0508588B1 (ko)
JP (1) JPH04311900A (ko)
KR (1) KR950010300B1 (ko)
DE (1) DE69222560T2 (ko)
TW (1) TW222030B (ko)

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Also Published As

Publication number Publication date
EP0508588A3 (ko) 1994-04-13
KR950010300B1 (ko) 1995-09-14
DE69222560T2 (de) 1998-04-16
DE69222560D1 (de) 1997-11-13
US5268861A (en) 1993-12-07
EP0508588A2 (en) 1992-10-14
JPH04311900A (ja) 1992-11-04
EP0508588B1 (en) 1997-10-08
TW222030B (ko) 1994-04-01

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