KR900002564A - 스탠다드셀 - Google Patents

스탠다드셀 Download PDF

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Publication number
KR900002564A
KR900002564A KR1019890010200A KR890010200A KR900002564A KR 900002564 A KR900002564 A KR 900002564A KR 1019890010200 A KR1019890010200 A KR 1019890010200A KR 890010200 A KR890010200 A KR 890010200A KR 900002564 A KR900002564 A KR 900002564A
Authority
KR
South Korea
Prior art keywords
flip
cell row
flop
clock wiring
standard
Prior art date
Application number
KR1019890010200A
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English (en)
Other versions
KR920010213B1 (ko
Inventor
도루 사사키
다케지 도쿠마루
츠네아키 구도
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 익렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 익렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR900002564A publication Critical patent/KR900002564A/ko
Application granted granted Critical
Publication of KR920010213B1 publication Critical patent/KR920010213B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음

Description

스탠다드 셀
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 실시예에 따른 스탠다드셀을 구성을 나타낸 도면,
제 2 도(A)는 클럭스큐의 발생을 설명하는 회로도,
제 2 도(B)는 레이싱현상을 방지하는 회로도.

Claims (5)

  1. 복수의 플립플롭회로(FF) 및 그외의 복수의 논리회로영역(13)을 포함하는 복수행의 스탠다드셀에 있어서, 상기 플립플롭회로(FF)를 모두 특정한 1개의 셀행(12 ; 플립플롭회로영역)에 배치하고, 상기 특정한 셀행(12)에 대해 전용의 클럭배선영역(11)을 설치해서 최단인출선(l1~ln)을 매개로 상기 클럭배선영역(11)의 클럭배선과 상기 각 플립플럽회로(FF)를 접속하도록 된 것을 특징으로 하는 스탠다드셀.
  2. 제 1 항에 있어서, 상기 플립플롭회로(FF)가 상기 특정한 셀행(12)에서 1군(群)으로 정렬된 형태로 인접되게 배치된 것을 특징으로 하는 스탠다드셀.
  3. 제 1 항에 있어서, 상기 클럭배선영역(11)이 상기 특정한 셀행(12)에 대해 평행하게 배치된 것을 특징으로 하는 스탠다드셀.
  4. 제 3 항에 있어서, 상기 클럭배선영역(11)과 각 플립플롭회로(FF)를 접속시키기 위한 인출선(l1~ln)이 모두 동일한 길이로 된 것을 특징으로 하는 스탠다드셀.
  5. 플립플롭회로군(FF群) 및 그외의 논리회로영역(13)을 포함하는 복수행의 스탠다드셀에 있어서, 상기 플립플롭회로군을 특정한 1개의 셀행(12)에 정렬시켜 집중배치함과 더불어, 클럭배선(l1,l2,l3,…)을 상기 플립플롭회로군이 배치된 셀행(12)내에 설치한 것을 특징으로 하는 스탠다드셀.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890010200A 1988-07-19 1989-07-19 스탠다드셀 KR920010213B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63178214A JPH0229124A (ja) 1988-07-19 1988-07-19 スタンダードセル
JP88-178214 1988-07-19

Publications (2)

Publication Number Publication Date
KR900002564A true KR900002564A (ko) 1990-02-28
KR920010213B1 KR920010213B1 (ko) 1992-11-21

Family

ID=16044580

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890010200A KR920010213B1 (ko) 1988-07-19 1989-07-19 스탠다드셀

Country Status (5)

Country Link
US (1) US5029279A (ko)
EP (1) EP0351819B1 (ko)
JP (1) JPH0229124A (ko)
KR (1) KR920010213B1 (ko)
DE (1) DE68924213T2 (ko)

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JP2622612B2 (ja) * 1989-11-14 1997-06-18 三菱電機株式会社 集積回路
JPH03257949A (ja) * 1990-03-06 1991-11-18 Advanced Micro Devices Inc 遅延回路
US5208764A (en) * 1990-10-29 1993-05-04 Sun Microsystems, Inc. Method for optimizing automatic place and route layout for full scan circuits
TW198159B (ko) * 1991-05-31 1993-01-11 Philips Gloeicampenfabrieken Nv
JP3026387B2 (ja) * 1991-08-23 2000-03-27 沖電気工業株式会社 半導体集積回路
US5396129A (en) * 1992-05-25 1995-03-07 Matsushita Electronics Corporation Semiconductor integrated circuit apparatus comprising clock signal line formed in a ring shape
US5508938A (en) * 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
US5387825A (en) * 1992-08-20 1995-02-07 Texas Instruments Incorporated Glitch-eliminator circuit
JP3048471B2 (ja) * 1992-09-08 2000-06-05 沖電気工業株式会社 クロック供給回路及びクロックスキュー調整方法
US5444407A (en) * 1992-12-28 1995-08-22 Advanced Micro Devices, Inc. Microprocessor with distributed clock generators
EP0613074B1 (en) * 1992-12-28 1998-04-01 Advanced Micro Devices, Inc. Microprocessor circuit having two timing signals
US5444406A (en) * 1993-02-08 1995-08-22 Advanced Micro Devices, Inc. Self-adjusting variable drive strength buffer circuit and method for controlling the drive strength of a buffer circuit
DE4422784C2 (de) * 1994-06-29 1999-05-27 Texas Instruments Deutschland Schaltungsanordnung mit wenigstens einer Schaltungseinheit wie einem Register, einer Speicherzelle, einer Speicheranordnung oder dergleichen
US5742832A (en) * 1996-02-09 1998-04-21 Advanced Micro Devices Computer system with programmable driver output's strengths responsive to control signal matching preassigned address range
US6211703B1 (en) * 1996-06-07 2001-04-03 Hitachi, Ltd. Signal transmission system
JPH11186506A (ja) * 1997-12-24 1999-07-09 Mitsubishi Electric Corp 集積回路
JP2007299800A (ja) 2006-04-27 2007-11-15 Nec Electronics Corp 半導体集積回路装置
US8018052B2 (en) * 2007-06-29 2011-09-13 Stats Chippac Ltd. Integrated circuit package system with side substrate having a top layer
JP2009152822A (ja) * 2007-12-20 2009-07-09 Spansion Llc 記憶装置
US11095272B2 (en) * 2018-09-21 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Flip-flop cell

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3747064A (en) * 1971-06-30 1973-07-17 Ibm Fet dynamic logic circuit and layout
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
JPS55115352A (en) * 1979-02-27 1980-09-05 Fujitsu Ltd Clock distributing circuit of ic device
JPS5969948A (ja) * 1982-10-15 1984-04-20 Fujitsu Ltd マスタ−スライス型半導体集積回路
US4694403A (en) * 1983-08-25 1987-09-15 Nec Corporation Equalized capacitance wiring method for LSI circuits
JPS6341048A (ja) * 1986-08-06 1988-02-22 Mitsubishi Electric Corp 標準セル方式大規模集積回路
JPH0815210B2 (ja) * 1987-06-04 1996-02-14 日本電気株式会社 マスタスライス方式集積回路
JPH0828421B2 (ja) * 1987-08-27 1996-03-21 株式会社東芝 半導体集積回路装置

Also Published As

Publication number Publication date
DE68924213T2 (de) 1996-04-04
JPH0481895B2 (ko) 1992-12-25
EP0351819A2 (en) 1990-01-24
EP0351819A3 (en) 1990-11-28
DE68924213D1 (de) 1995-10-19
US5029279A (en) 1991-07-02
KR920010213B1 (ko) 1992-11-21
JPH0229124A (ja) 1990-01-31
EP0351819B1 (en) 1995-09-13

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