KR910020896A - 반도체집적회로 - Google Patents

반도체집적회로 Download PDF

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Publication number
KR910020896A
KR910020896A KR1019910008414A KR910008414A KR910020896A KR 910020896 A KR910020896 A KR 910020896A KR 1019910008414 A KR1019910008414 A KR 1019910008414A KR 910008414 A KR910008414 A KR 910008414A KR 910020896 A KR910020896 A KR 910020896A
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KR
South Korea
Prior art keywords
power supply
circuit
cmos
lines
spaced apart
Prior art date
Application number
KR1019910008414A
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English (en)
Other versions
KR950010202B1 (ko
Inventor
가츠히로 세타
히로유키 하라
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910020896A publication Critical patent/KR910020896A/ko
Application granted granted Critical
Publication of KR950010202B1 publication Critical patent/KR950010202B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 셀라이브러리(cell library)를 사용한 집적회로를 나타낸 평면도, 제2도는 본 발명에 따른 게이트어레이셀의 구체예에 나타낸 평면도.

Claims (3)

  1. 서로 이격되어 형성된 2개의 전원선(5, 7)과 그 사이에 형성된 CMOS회로(9)로 이루어진 CMOS셀(3)과, 상기 2개의 전원선(5, 7)과 동일한 간격으로 이간된 2개의 전원선(5, 7)과 그사이에 형성된 CMOS회로(13) 및 이 전원선(5, 7)의 외측에 형성된 바이폴라트랜지스터회로(15)로 이루어진 BiCMOS셀(11)을 구비한 것을 특징으로 하는 반도체집적회로.
  2. 제1항에 있어서, 상기 BiCMOS셀(11)은 출력부분에 바이폴라트랜지스터회로를 사용한 논리회로인 것을 특징으로 하는 반도체집적회로.
  3. 서로 이격되어 형성된 2개의 전원선(25, 27)과 그 사이에 형성된 CMOS회로로 이루어진 CMOS회로로 이루어진 CMOS셀(29)과, 상기 2개의 전원선(25, 27)보다 넓은 간격으로 이간된 2개의 전원선(31, 33)과 그사이에 형성된 CMOS회로 및 바이폴라트랜지스터회로로 이루어진 BiCMOS셀 및, 상기 BiCMOS셀의 전원선과 접속되고, 이것과 동일한 간격으로 평행하게 연장되어 상기 CMOS셀(29)의 전원선(25, 27)과 접속된 2개의 전원선(31, 33)을 구비한 것을 특징으로 하는 반도체집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910008414A 1990-05-24 1991-05-24 반도체집적회로 KR950010202B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP02-132497 1990-05-24
JP2132497A JP2505910B2 (ja) 1990-05-24 1990-05-24 半導体集積回路用セルライブラリ

Publications (2)

Publication Number Publication Date
KR910020896A true KR910020896A (ko) 1991-12-20
KR950010202B1 KR950010202B1 (ko) 1995-09-11

Family

ID=15082757

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910008414A KR950010202B1 (ko) 1990-05-24 1991-05-24 반도체집적회로

Country Status (5)

Country Link
US (1) US5387810A (ko)
EP (1) EP0458244B1 (ko)
JP (1) JP2505910B2 (ko)
KR (1) KR950010202B1 (ko)
DE (1) DE69125203T2 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5798541A (en) * 1994-12-02 1998-08-25 Intel Corporation Standard semiconductor cell with contoured cell boundary to increase device density
US5682323A (en) 1995-03-06 1997-10-28 Lsi Logic Corporation System and method for performing optical proximity correction on macrocell libraries
US5768146A (en) * 1995-03-28 1998-06-16 Intel Corporation Method of cell contouring to increase device density
US5724251A (en) * 1995-06-07 1998-03-03 Advanced Micro Devices, Inc. System and method for designing, fabricating and testing multiple cell test structures to validate a cell library
GB2384877B (en) * 2002-02-01 2004-12-15 Micron Technology Inc System and method for generating high-quality libraries
JP4056348B2 (ja) * 2002-10-07 2008-03-05 株式会社ルネサステクノロジ 集積回路チップモジュールおよび携帯電話機
JP2005027041A (ja) 2003-07-02 2005-01-27 Renesas Technology Corp 固体撮像装置
US8390331B2 (en) * 2009-12-29 2013-03-05 Nxp B.V. Flexible CMOS library architecture for leakage power and variability reduction
JP5918833B1 (ja) * 2014-11-12 2016-05-18 株式会社ホワイトハウス 座席回転装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5827343A (ja) * 1981-08-10 1983-02-18 Matsushita Electronics Corp 半導体集積回路
US4575745A (en) * 1983-06-21 1986-03-11 Rca Corporation Tailorable standard cells and method for tailoring the performance of IC designs
CN1003549B (zh) * 1985-01-25 1989-03-08 株式会社日立制作所 半导体集成电路器件
JPH0815209B2 (ja) * 1985-01-25 1996-02-14 株式会社日立製作所 半導体集積回路装置
JPH0732194B2 (ja) * 1986-05-23 1995-04-10 日本電気株式会社 Ｍｏｓ集積回路
JPS63197356A (ja) * 1987-02-12 1988-08-16 Matsushita Electric Ind Co Ltd 集積回路装置
JPH0831581B2 (ja) * 1988-02-19 1996-03-27 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
EP0458244A2 (en) 1991-11-27
JP2505910B2 (ja) 1996-06-12
EP0458244A3 (en) 1992-01-22
DE69125203T2 (de) 1997-08-07
JPH0428264A (ja) 1992-01-30
US5387810A (en) 1995-02-07
EP0458244B1 (en) 1997-03-19
KR950010202B1 (ko) 1995-09-11
DE69125203D1 (de) 1997-04-24

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