KR840004308A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

Info

Publication number
KR840004308A
KR840004308A KR1019830000925A KR830000925A KR840004308A KR 840004308 A KR840004308 A KR 840004308A KR 1019830000925 A KR1019830000925 A KR 1019830000925A KR 830000925 A KR830000925 A KR 830000925A KR 840004308 A KR840004308 A KR 840004308A
Authority
KR
South Korea
Prior art keywords
region
conductive type
area
word line
collector
Prior art date
Application number
KR1019830000925A
Other languages
English (en)
Other versions
KR900008622B1 (ko
Inventor
겐지(외 2) 가네고
Original Assignee
미쓰다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미쓰다 가쓰시게, 가부시기가이샤 히다찌세이사꾸쇼 filed Critical 미쓰다 가쓰시게
Publication of KR840004308A publication Critical patent/KR840004308A/ko
Application granted granted Critical
Publication of KR900008622B1 publication Critical patent/KR900008622B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/10—SRAM devices comprising bipolar components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 실시예를 도시한 도면.

Claims (5)

  1. 각각이 제1도전형의 에미터 영역, 과 상기 에미터 영역내의 제2도전형의 베이스 영역, 과 그리고,상기 베이스 영역내의 제1도전형의 제1, 제2콜렉터 영역, 그리고, 또 상기 에미터 영역내에서 상기 케이스 영역과는 독립되어 설치된 제2도전형의 각각 인젝터 영역을 포함하는 제1, 제2의 IIL 단의 회로로 되고, 또, 각각 제1의 콜렉터 영역과 베이스 영역은과는 서로 교차 결합된 제1, 제2의 IIL단위 회로를 포함하는 메모리셀과, 상기 제1, 제2의 IIL 단위 회로의 제2콜렉터 영역에 각각 접속되고, 각각의 부하소자를 거쳐서 상기 제2콜렉터 영역, 과 상기의 베이스 영역, 그리고 상기의 에미터 영역에 의하여 형성되는 역방향 트랜지스터를 역방향 동작시키기 위한 전원에 접속된 쌍을 이루고 있는 비트선을과를 갖는 반도체 기억장치.
  2. 상기의 제1도전형은 P형, 상기 제2도전형은 N형인 것을 특징으로 하는 특허 청구 범위 제1의 반도체 기억장치.
  3. 상기의 인젝터 영역은 윗쪽의 워드선에 접속되고 상기의 에미터 영역은 아랫쪽의 워드선에 접속되는 것을 특징으로 하는 특허 청구의 범위 제2의 반도체 기억장치.
  4. 상기의 전원은 상기 아랫쪽의 워드선의 전압보다 높은 전압을 갖도록 하는 것을 특징으로 하는 특허 청구의 범위 3의 반도체 기억장치.
  5. 상기의 부하소자는 저항인 것을 특징으로 하는 특허 청구 범위 제1의 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830000925A 1982-03-17 1983-03-08 반도체 기억장치 KR900008622B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP57040786A JPS58159294A (ja) 1982-03-17 1982-03-17 半導体記憶装置
JP40786 1982-03-17
JP57-40786 1982-03-17

Publications (2)

Publication Number Publication Date
KR840004308A true KR840004308A (ko) 1984-10-10
KR900008622B1 KR900008622B1 (ko) 1990-11-26

Family

ID=12590299

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830000925A KR900008622B1 (ko) 1982-03-17 1983-03-08 반도체 기억장치

Country Status (5)

Country Link
US (1) US4589096A (ko)
JP (1) JPS58159294A (ko)
KR (1) KR900008622B1 (ko)
DE (1) DE3305026A1 (ko)
GB (1) GB2117201B (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6025907B2 (ja) * 1981-11-20 1985-06-20 富士通株式会社 半導体記憶装置
JPS6376193A (ja) * 1986-09-19 1988-04-06 Fujitsu Ltd 半導体記憶装置
JPS6376192A (ja) * 1986-09-19 1988-04-06 Fujitsu Ltd 半導体記憶装置
JP2555039B2 (ja) * 1986-11-12 1996-11-20 株式会社日立製作所 半導体集積回路装置
JPH0828423B2 (ja) * 1988-10-14 1996-03-21 日本電気株式会社 半導体記憶装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3815106A (en) * 1972-05-11 1974-06-04 S Wiedmann Flip-flop memory cell arrangement
US3936813A (en) * 1973-04-25 1976-02-03 Intel Corporation Bipolar memory cell employing inverted transistors and pinched base resistors
US4150392A (en) * 1976-07-31 1979-04-17 Nippon Gakki Seizo Kabushiki Kaisha Semiconductor integrated flip-flop circuit device including merged bipolar and field effect transistors
DE2964801D1 (en) * 1978-06-30 1983-03-24 Fujitsu Ltd Semiconductor integrated circuit device
DE3070152D1 (en) * 1979-07-26 1985-03-28 Fujitsu Ltd Semiconductor memory device including integrated injection logic memory cells
JPS5847792B2 (ja) * 1979-07-26 1983-10-25 富士通株式会社 ビット線制御回路
EP0030422B1 (en) * 1979-11-28 1987-05-27 Fujitsu Limited Semiconductor memory circuit device

Also Published As

Publication number Publication date
GB2117201A (en) 1983-10-05
JPS58159294A (ja) 1983-09-21
KR900008622B1 (ko) 1990-11-26
DE3305026A1 (de) 1983-09-29
GB2117201B (en) 1985-10-02
US4589096A (en) 1986-05-13
GB8304331D0 (en) 1983-03-23

Similar Documents

Publication Publication Date Title
KR880000965A (ko) 반도체 기억장치
KR890004321A (ko) 로직마크로 및 랜덤억세스메모리 마크로를 구비한 반도체 집적회로장치
KR850004879A (ko) 반도체 메모리
KR890016573A (ko) 반도체기억장치
KR900010998A (ko) 반도체 집적회로 장치
KR840002176A (ko) 반도체 집적회로 장치
KR850004877A (ko) 배선 지연이 적은 배선 및 데코우더를 가진 반도체 메모리
KR930005020A (ko) 망사 구조의 전원선을 가지는 반도체 메모리 장치
KR950010098A (ko) 반도체 기억장치
KR860007750A (ko) 반도체 장치
KR880002270A (ko) 대규모 집적회로용 보호회로
KR870010550A (ko) 바이폴라 및 mos 장치를 갖춘 트랜스리니어 스태틱 메모리 셀
KR930003381A (ko) 전압 리미터 회로를 갖는 반도체 집적 회로
KR910008836A (ko) 반도체기억장치
KR840004308A (ko) 반도체 기억장치
KR890004333A (ko) 반도체 메모리 장치
KR920007194A (ko) 표준 셀 방식의 반도체 집접회로
KR900019041A (ko) 반도체 메모리
KR850008239A (ko) 반도체 기억장치
KR910020896A (ko) 반도체집적회로
KR870002584A (ko) 반도체 메모리 장치
KR850007179A (ko) 집적 논리회로
KR890007406A (ko) 고밀도 집적회로
GB1490724A (en) Complementary storage elements in integrated circuits
KR850004355A (ko) 직열 접속 트랜지스터를 가진 반도체 집적회로

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19941115

Year of fee payment: 5

LAPS Lapse due to unpaid annual fee