KR890007406A - 고밀도 집적회로 - Google Patents

고밀도 집적회로 Download PDF

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Publication number
KR890007406A
KR890007406A KR1019880013051A KR880013051A KR890007406A KR 890007406 A KR890007406 A KR 890007406A KR 1019880013051 A KR1019880013051 A KR 1019880013051A KR 880013051 A KR880013051 A KR 880013051A KR 890007406 A KR890007406 A KR 890007406A
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KR
South Korea
Prior art keywords
gate electrode
electrode wiring
wiring
high density
density integrated
Prior art date
Application number
KR1019880013051A
Other languages
English (en)
Other versions
KR910009423B1 (ko
Inventor
에이찌 미나미
Original Assignee
미따 가쓰시게
가부시끼가이샤 히다찌 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미따 가쓰시게, 가부시끼가이샤 히다찌 세이사꾸쇼 filed Critical 미따 가쓰시게
Publication of KR890007406A publication Critical patent/KR890007406A/ko
Application granted granted Critical
Publication of KR910009423B1 publication Critical patent/KR910009423B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

고밀도 집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일 실시예인 반도체 소자상에 형성된 LSI의 구성을 나타내는 설명도.
제2도는 상기 실시예에서의 다층배선의 일 구성예를 나타내는 설명도.
* 도면의 주요부분에 대한 부호의 설명
1 : 반도체기판 2 : 기본셀
4 : 논리셀 5 : 여영역
6 : 제1층 금속배선 7 : 제2층 금속배선
8 : 관통공 10 : 게이트전극배선
14, 15, 16 : 배선로 18 : 전원배선
19 : 접지배선

Claims (4)

  1. 반도체기판; 상기 반도체기판상에 배치된 적어도 한쌍의 p-형 MOS트랜지스터와 n-형 MOS트랜지스터 및 게이트전극배선을 갖는 복수개의 기본셀을 조합함으로써 구성되어 지는 논리셀; 상기 반도체기판상에 상기 논리셀을 포함하지 않는 여영역; 상기 여영역에 연설되는 연설되는 상기 게이트전극배선의 연설부; 상기 여영역에서, 상기 게이트전극배선의 상기 연설부가 속하는 층과 다른 층에 배치된 배선부; 및 상기 게이트전극배선의 상기 연설부와 그것과 다른 층에 배치된 상기 배선부를 접속시키는 관통공 등을 구성하는 고밀도 집적회로.
  2. 제1항에 있어서, 상기 기본셀이 게이트에레이방식으로 구성되는 고밀도 집적회로.
  3. 제1항에 있어서, 상기 다른 층의 배선부가 2층 이상에 배치되는 고밀도 집적회로.
  4. 제1항에 있어서, 상기 게이트 전극배선의 연설부가 통상의 게이트전극배선보다 폭이 넓은 고밀도 집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880013051A 1987-10-06 1988-10-06 고밀도 집적회로 KR910009423B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62251963A JPH0194636A (ja) 1987-10-06 1987-10-06 半導体装置
JP62-251963 1987-10-06

Publications (2)

Publication Number Publication Date
KR890007406A true KR890007406A (ko) 1989-06-19
KR910009423B1 KR910009423B1 (ko) 1991-11-15

Family

ID=17230591

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880013051A KR910009423B1 (ko) 1987-10-06 1988-10-06 고밀도 집적회로

Country Status (3)

Country Link
US (1) US4949157A (ko)
JP (1) JPH0194636A (ko)
KR (1) KR910009423B1 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0831458B2 (ja) * 1987-09-08 1996-03-27 三菱電機株式会社 超電導配線集積回路
US5168342A (en) * 1989-01-30 1992-12-01 Hitachi, Ltd. Semiconductor integrated circuit device and manufacturing method of the same
SG67297A1 (en) * 1989-04-19 1999-09-21 Seiko Epson Corp Semiconductor device
JPH0828120B2 (ja) * 1990-05-23 1996-03-21 株式会社東芝 アドレスデコード回路
US5079614A (en) * 1990-09-26 1992-01-07 S-Mos Systems, Inc. Gate array architecture with basic cell interleaved gate electrodes
JP3556814B2 (ja) * 1997-10-23 2004-08-25 株式会社ルネサステクノロジ フィールドシールド分離トランジスタ
KR100525111B1 (ko) * 2004-04-19 2005-11-01 주식회사 하이닉스반도체 반도체 소자

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3477312D1 (de) * 1983-07-09 1989-04-20 Fujitsu Ltd Masterslice semiconductor device
JPS6135535A (ja) * 1984-07-27 1986-02-20 Fujitsu Ltd マスタ−スライス集積回路装置
JPH0693480B2 (ja) * 1985-03-29 1994-11-16 株式会社東芝 半導体集積回路装置
JPH0789568B2 (ja) * 1986-06-19 1995-09-27 日本電気株式会社 集積回路装置

Also Published As

Publication number Publication date
KR910009423B1 (ko) 1991-11-15
JPH0194636A (ja) 1989-04-13
US4949157A (en) 1990-08-14

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