KR910003801A - 반도체 집적회로장치 및 그 제조방법 - Google Patents

반도체 집적회로장치 및 그 제조방법 Download PDF

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Publication number
KR910003801A
KR910003801A KR1019900011110A KR900011110A KR910003801A KR 910003801 A KR910003801 A KR 910003801A KR 1019900011110 A KR1019900011110 A KR 1019900011110A KR 900011110 A KR900011110 A KR 900011110A KR 910003801 A KR910003801 A KR 910003801A
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KR
South Korea
Prior art keywords
integrated circuit
semiconductor integrated
wiring
power supply
circuit device
Prior art date
Application number
KR1019900011110A
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English (en)
Other versions
KR930009023B1 (ko
Inventor
사토시 와다
시니치 와카바야시
마사요 후지타
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910003801A publication Critical patent/KR910003801A/ko
Application granted granted Critical
Publication of KR930009023B1 publication Critical patent/KR930009023B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

내용 없음.

Description

반도체집적회로장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명의 각 실시예를 나타낸 패턴 평면도.

Claims (3)

  1. 반도체집적회로의 셀간배선(8)과 동일한 폭과 배선피치로 형성되고, 상기 반도체집적회로칩의 기판전위(VDD)와 역전위인 내부전원(VSS)에 접속된 더미배선(4)을 구비하여 구성된 것을 특징으로 하는 반도체집적회로장치.
  2. 반도체집적회로의 셀간배선(8)과 동일한 폭과 배선피치로 형성되고, 상기 반도체집적회로칩의 기판전위(VDD)와 역전위인 내부전원(VSS)에 접속된 더미배선(4)을 상기 내부전원(VSS)에 전기적으로 절단하여 절단부(11)를 형성하고, 이 절단선 더미배선(41)을 오배선의 수정에 이용하는 것을 특징으로 하는 반도체집적회로장치의 제조방법.
  3. 반도체집적회로의 셀간배선(8)과 동일한 폭과 배선피치로 형성되고, 상기 반도체집적회로칩의 기판전위(VDD)와 역전위인 내부전원(VSS)에 접속된 더미배선(4)을 상기 내부전원(VSS)에 전기적으로 절단하여 절단부(11)를 형성하고, 이 절단선 더미배선(42)을 신호지연의 보정에 이용하는 것을 특징으로 하는 반도체집적회로장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900011110A 1989-07-21 1990-07-21 반도체집적회로장치 및 그 제조방법 KR930009023B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1189312A JP2507618B2 (ja) 1989-07-21 1989-07-21 半導体集積回路装置の製造方法
JP1-189312 1989-07-21
JP01-189312 1989-07-21

Publications (2)

Publication Number Publication Date
KR910003801A true KR910003801A (ko) 1991-02-28
KR930009023B1 KR930009023B1 (ko) 1993-09-18

Family

ID=16239245

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900011110A KR930009023B1 (ko) 1989-07-21 1990-07-21 반도체집적회로장치 및 그 제조방법

Country Status (5)

Country Link
US (1) US5160995A (ko)
EP (1) EP0409256B1 (ko)
JP (1) JP2507618B2 (ko)
KR (1) KR930009023B1 (ko)
DE (1) DE69034109T2 (ko)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396100A (en) * 1991-04-05 1995-03-07 Hitachi, Ltd. Semiconductor integrated circuit device having a compact arrangement of SRAM cells
JPH0851159A (ja) * 1994-08-05 1996-02-20 Mitsubishi Electric Corp 半導体集積回路
JP3180612B2 (ja) * 1995-03-27 2001-06-25 ヤマハ株式会社 半導体集積回路
US5814847A (en) * 1996-02-02 1998-09-29 National Semiconductor Corp. General purpose assembly programmable multi-chip package substrate
JP3159108B2 (ja) * 1997-03-27 2001-04-23 ヤマハ株式会社 半導体装置とその製造方法
US5917230A (en) * 1997-04-09 1999-06-29 United Memories, Inc. Filter capacitor construction
DE19825607C2 (de) * 1998-06-08 2000-08-10 Siemens Ag Integrierte Halbleiterschaltung mit Füllstrukturen
JP4598470B2 (ja) * 1998-07-03 2010-12-15 パナソニック株式会社 半導体装置
US6346427B1 (en) 1999-08-18 2002-02-12 Utmc Microelectronic Systems Inc. Parameter adjustment in a MOS integrated circuit
US6323113B1 (en) * 1999-12-10 2001-11-27 Philips Electronics North America Corporation Intelligent gate-level fill methods for reducing global pattern density effects
WO2005117115A1 (en) * 2004-05-28 2005-12-08 Koninklijke Philips Electronics N.V. Chips with useful lines and dummy lines
JP4364226B2 (ja) * 2006-09-21 2009-11-11 株式会社東芝 半導体集積回路
US11239154B2 (en) * 2015-01-20 2022-02-01 Taiwan Semiconductor Manufacturing Company Ltd. Fishbone structure enhancing spacing with adjacent conductive line in power network
US10523188B2 (en) 2016-02-23 2019-12-31 Samsung Electronics Co., Ltd. Semiconductor device

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5852346B2 (ja) * 1977-02-18 1983-11-22 株式会社東芝 半導体装置
JPS59198796A (ja) * 1983-04-26 1984-11-10 日本電気株式会社 高密度多層配線基板
JPS60119749A (ja) * 1983-12-02 1985-06-27 Hitachi Ltd 多層配線部材
JPH0658947B2 (ja) * 1984-02-24 1994-08-03 株式会社日立製作所 半導体メモリ装置の製法
JPS61125045A (ja) * 1984-11-22 1986-06-12 Hitachi Ltd 半導体装置
JPS6218732A (ja) * 1985-07-15 1987-01-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 集積回路とその個性化方法
JPS62206855A (ja) * 1986-03-06 1987-09-11 Nec Corp 半導体装置の配線構造
JPS6387744A (ja) * 1986-09-30 1988-04-19 Nec Corp 半導体集積回路
JPS63304496A (ja) * 1987-06-03 1988-12-12 Mitsubishi Electric Corp 半導体記憶装置
US4916514A (en) * 1988-05-31 1990-04-10 Unisys Corporation Integrated circuit employing dummy conductors for planarity
JPH021928A (ja) * 1988-06-10 1990-01-08 Toshiba Corp 半導体集積回路

Also Published As

Publication number Publication date
JP2507618B2 (ja) 1996-06-12
EP0409256A3 (en) 1992-10-14
DE69034109D1 (de) 2003-11-20
EP0409256B1 (en) 2003-10-15
EP0409256A2 (en) 1991-01-23
KR930009023B1 (ko) 1993-09-18
US5160995A (en) 1992-11-03
DE69034109T2 (de) 2004-07-29
JPH0353547A (ja) 1991-03-07

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