KR910001975A - 반도체장치 및 그 번인방법 - Google Patents

반도체장치 및 그 번인방법 Download PDF

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Publication number
KR910001975A
KR910001975A KR1019900009729A KR900009729A KR910001975A KR 910001975 A KR910001975 A KR 910001975A KR 1019900009729 A KR1019900009729 A KR 1019900009729A KR 900009729 A KR900009729 A KR 900009729A KR 910001975 A KR910001975 A KR 910001975A
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South Korea
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semiconductor device
wirings
wiring
chip
chip regions
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KR1019900009729A
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KR940006577B1 (ko
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도루 후루야마
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아오이 죠이치
가부시키가이샤 도시바
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Geometry (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체장치 및 그 번인방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 반도체장치의 1실시예를 개략적으로 나타낸 구성설명도.
제2도는 제1도중의 일부를 추출해서 공통배선과 각 칩영역과의 접속예를 나타낸 회로도.
제3도는 본 발명의 반도체장치의 다른 실시예를 개략적으로 나타낸 구성설명도.
제4도는 제1도 또는 제3도중의 1개의 다이나믹 RAM의 칩 영역에 있어서 일부의 회로를 추출해서 공통배선과의 접속예를 나타낸 회로도.

Claims (12)

  1. 복수개의 집접회로의 칩영역(11)을 갖춘 웨이퍼상태의 반도체장치(10)에 있어서, 상기 복수개의 칩영역(11)에 공통으로 접속된 배선(12,13)이 형성되어 있는 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 배선(12,13)이 집적회로의 칩영역(11)의 회로를 구동하기 위한 전원선 및 집적회로의 칩영역(11)의 동작을 제어하기 위한 신호선인 것을 특징으로 하는 반도체장치.
  3. 제1항에 있어서, 상기 배선(12,13)에 웨이퍼의 외부에서 전원전압 및 신호를 인가하기 위한 접촉영역(12″, 13″)이 형성되어 있는 것을 특징으로 하는 반도체장치.
  4. 제1항에 있어서, 상기 복수개의 집적회로의 칩영역(11)이 개개로 분할되어 집적회로로서 조립되는 것을 특징으로 하는 반도체장치.
  5. 제1항에 있어서, 상기 배선(12,13)이 단층 또는 다층의 배선으로 이루어진 것을 특징으로 하는 반도체장치.
  6. 제1항 내지 제5항중의 어느 한 항에 있어서, 상기 배선(12,13)의 전부 또는 일부가 각 칩영역911)의 내부에서 사용되고 있는 배선과 동일한 배선층에 의해 웨이퍼의 절단선상에 형성되어 있는 것을 특징으로 하는 반도체장치.
  7. 제6항에 있어서, 상기 배선(12,13)과 각 칩영역(11)의 내부에서 사용되고 있는 배선간의 접속이 칩영역(11)을 다이로 잘라내기 전에 절단되는 것을 특징으로 하는 반도체장치.
  8. 제1항 내지 제5항중의 어느 한 항에 있어서, 상기 배선(12,13)의 전부 또는 일부가 별도로 새롭게 부가한 배선층에 의해 형성되어 있는 것을 특징으로 하는 반도체장치.
  9. 제8항에 있어서, 상기 배선(12,13)이 칩영역(11)을 다이로 잘라내기 전에 제거되는 것을 특징으로 하는 반도체장치.
  10. 제1항 내지 제5항중의 어느 한 항에 있어서, 사기 배선(12,13)과 각 칩영역(11)의 내부에서 사용되고 있는 배선간에 저항소자(r)가 삽입되어 있는 것을 특징으로 하는 반도체장치.
  11. 제10항에 있어서, 상기 저항소자(r)의 저항치가 상기 배선(12,13)의 시트저항보다 높게 설정되어 있는 것을 특징으로 하는 반도체장치.
  12. 반도체장치의 번인방법에 있어서, 복수개의 집적회로에 칩영역(11)을 갖추고 있고, 상기 복수개의 칩영역(11)에 공통으로 접속된 배선(12,13)을 갖춘 웨이퍼상태의 반도체장치(10)를 준비하여 상기 공통배선(12,13)에 전원전압 및 신호를 인가함으로써 번인을 행하는 것을 특징으로 하는 반도체장치의 번인방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900009729A 1989-06-30 1990-06-29 반도체장치 및 그 번인방법 KR940006577B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1169659A JP2585799B2 (ja) 1989-06-30 1989-06-30 半導体メモリ装置及びそのバーンイン方法
JP1-169659 1989-06-30

Publications (2)

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KR910001975A true KR910001975A (ko) 1991-01-31
KR940006577B1 KR940006577B1 (ko) 1994-07-22

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US (2) US5138427A (ko)
EP (1) EP0405586B1 (ko)
JP (1) JP2585799B2 (ko)
KR (1) KR940006577B1 (ko)
DE (1) DE69030283T2 (ko)

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JP2585799B2 (ja) 1997-02-26
JPH0334555A (ja) 1991-02-14
DE69030283D1 (de) 1997-04-30
KR940006577B1 (ko) 1994-07-22
DE69030283T2 (de) 1997-08-07
EP0405586B1 (en) 1997-03-26
EP0405586A1 (en) 1991-01-02
US5138427A (en) 1992-08-11
US5294776A (en) 1994-03-15

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