KR910001975A - 반도체장치 및 그 번인방법 - Google Patents

반도체장치 및 그 번인방법 Download PDF

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Publication number
KR910001975A
KR910001975A KR1019900009729A KR900009729A KR910001975A KR 910001975 A KR910001975 A KR 910001975A KR 1019900009729 A KR1019900009729 A KR 1019900009729A KR 900009729 A KR900009729 A KR 900009729A KR 910001975 A KR910001975 A KR 910001975A
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South Korea
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semiconductor device
wirings
wiring
chip
chip regions
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KR1019900009729A
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KR940006577B1 (ko
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도루 후루야마
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아오이 죠이치
가부시키가이샤 도시바
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Geometry (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Memories (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

반도체장치 및 그 번인방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 반도체장치의 1실시예를 개략적으로 나타낸 구성설명도.
제2도는 제1도중의 일부를 추출해서 공통배선과 각 칩영역과의 접속예를 나타낸 회로도.
제3도는 본 발명의 반도체장치의 다른 실시예를 개략적으로 나타낸 구성설명도.
제4도는 제1도 또는 제3도중의 1개의 다이나믹 RAM의 칩 영역에 있어서 일부의 회로를 추출해서 공통배선과의 접속예를 나타낸 회로도.

Claims (12)

  1. 복수개의 집접회로의 칩영역(11)을 갖춘 웨이퍼상태의 반도체장치(10)에 있어서, 상기 복수개의 칩영역(11)에 공통으로 접속된 배선(12,13)이 형성되어 있는 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 배선(12,13)이 집적회로의 칩영역(11)의 회로를 구동하기 위한 전원선 및 집적회로의 칩영역(11)의 동작을 제어하기 위한 신호선인 것을 특징으로 하는 반도체장치.
  3. 제1항에 있어서, 상기 배선(12,13)에 웨이퍼의 외부에서 전원전압 및 신호를 인가하기 위한 접촉영역(12″, 13″)이 형성되어 있는 것을 특징으로 하는 반도체장치.
  4. 제1항에 있어서, 상기 복수개의 집적회로의 칩영역(11)이 개개로 분할되어 집적회로로서 조립되는 것을 특징으로 하는 반도체장치.
  5. 제1항에 있어서, 상기 배선(12,13)이 단층 또는 다층의 배선으로 이루어진 것을 특징으로 하는 반도체장치.
  6. 제1항 내지 제5항중의 어느 한 항에 있어서, 상기 배선(12,13)의 전부 또는 일부가 각 칩영역911)의 내부에서 사용되고 있는 배선과 동일한 배선층에 의해 웨이퍼의 절단선상에 형성되어 있는 것을 특징으로 하는 반도체장치.
  7. 제6항에 있어서, 상기 배선(12,13)과 각 칩영역(11)의 내부에서 사용되고 있는 배선간의 접속이 칩영역(11)을 다이로 잘라내기 전에 절단되는 것을 특징으로 하는 반도체장치.
  8. 제1항 내지 제5항중의 어느 한 항에 있어서, 상기 배선(12,13)의 전부 또는 일부가 별도로 새롭게 부가한 배선층에 의해 형성되어 있는 것을 특징으로 하는 반도체장치.
  9. 제8항에 있어서, 상기 배선(12,13)이 칩영역(11)을 다이로 잘라내기 전에 제거되는 것을 특징으로 하는 반도체장치.
  10. 제1항 내지 제5항중의 어느 한 항에 있어서, 사기 배선(12,13)과 각 칩영역(11)의 내부에서 사용되고 있는 배선간에 저항소자(r)가 삽입되어 있는 것을 특징으로 하는 반도체장치.
  11. 제10항에 있어서, 상기 저항소자(r)의 저항치가 상기 배선(12,13)의 시트저항보다 높게 설정되어 있는 것을 특징으로 하는 반도체장치.
  12. 반도체장치의 번인방법에 있어서, 복수개의 집적회로에 칩영역(11)을 갖추고 있고, 상기 복수개의 칩영역(11)에 공통으로 접속된 배선(12,13)을 갖춘 웨이퍼상태의 반도체장치(10)를 준비하여 상기 공통배선(12,13)에 전원전압 및 신호를 인가함으로써 번인을 행하는 것을 특징으로 하는 반도체장치의 번인방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900009729A 1989-06-30 1990-06-29 반도체장치 및 그 번인방법 KR940006577B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-169659 1989-06-30
JP1169659A JP2585799B2 (ja) 1989-06-30 1989-06-30 半導体メモリ装置及びそのバーンイン方法

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KR910001975A true KR910001975A (ko) 1991-01-31
KR940006577B1 KR940006577B1 (ko) 1994-07-22

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US (2) US5138427A (ko)
EP (1) EP0405586B1 (ko)
JP (1) JP2585799B2 (ko)
KR (1) KR940006577B1 (ko)
DE (1) DE69030283T2 (ko)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7511520B2 (en) * 1990-08-29 2009-03-31 Micron Technology, Inc. Universal wafer carrier for wafer level die burn-in
US5663654A (en) * 1990-08-29 1997-09-02 Micron Technology, Inc. Universal wafer carrier for wafer level die burn-in
KR960007478B1 (ko) * 1990-12-27 1996-06-03 가부시키가이샤 도시바 반도체장치 및 반도체장치의 제조방법
JP2925337B2 (ja) * 1990-12-27 1999-07-28 株式会社東芝 半導体装置
EP0494782B1 (en) * 1991-01-11 1997-04-23 Texas Instruments Incorporated Wafer burn-in and test system and method of making the same
JPH04330755A (ja) * 1991-02-27 1992-11-18 Mitsubishi Electric Corp 半導体集積回路およびそのエージング装置
US5391984A (en) * 1991-11-01 1995-02-21 Sgs-Thomson Microelectronics, Inc. Method and apparatus for testing integrated circuit devices
US5279975A (en) * 1992-02-07 1994-01-18 Micron Technology, Inc. Method of testing individual dies on semiconductor wafers prior to singulation
US5424651A (en) * 1992-03-27 1995-06-13 Green; Robert S. Fixture for burn-in testing of semiconductor wafers, and a semiconductor wafer
US5519193A (en) * 1992-10-27 1996-05-21 International Business Machines Corporation Method and apparatus for stressing, burning in and reducing leakage current of electronic devices using microwave radiation
US5399505A (en) * 1993-07-23 1995-03-21 Motorola, Inc. Method and apparatus for performing wafer level testing of integrated circuit dice
US5594273A (en) * 1993-07-23 1997-01-14 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where test pads lie within integrated circuit die but overly no active circuitry for improved yield
US5654588A (en) * 1993-07-23 1997-08-05 Motorola Inc. Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
JPH07169807A (ja) * 1993-12-16 1995-07-04 Nippondenso Co Ltd 半導体ウェハ
DE4400118A1 (de) * 1994-01-04 1995-07-06 Siemens Ag Verfahren zum Durchführen von Burn-in-Prozeduren an Halbleiterchips
US6577148B1 (en) * 1994-08-31 2003-06-10 Motorola, Inc. Apparatus, method, and wafer used for testing integrated circuits formed on a product wafer
US5777486A (en) * 1994-10-03 1998-07-07 United Microelectronics Corporation Electromigration test pattern simulating semiconductor components
JP3734853B2 (ja) * 1995-06-27 2006-01-11 株式会社ルネサステクノロジ 半導体記憶装置
US5852581A (en) * 1996-06-13 1998-12-22 Micron Technology, Inc. Method of stress testing memory integrated circuits
JP3592885B2 (ja) * 1997-03-31 2004-11-24 シャープ株式会社 半導体集積回路装置
US5898706A (en) * 1997-04-30 1999-04-27 International Business Machines Corporation Structure and method for reliability stressing of dielectrics
US6233185B1 (en) 1997-08-21 2001-05-15 Micron Technology, Inc. Wafer level burn-in of memory integrated circuits
US7161175B2 (en) * 1997-09-30 2007-01-09 Jeng-Jye Shau Inter-dice signal transfer methods for integrated circuits
JPH11354721A (ja) 1998-06-04 1999-12-24 Mitsubishi Electric Corp 半導体装置
KR100313185B1 (ko) * 1998-09-29 2001-11-07 포만 제프리 엘 집적 회로 소자의 전기적 액세스 및 상호 접속 방법과 그 장치
EP1031042B1 (de) * 1998-11-02 2001-06-20 ATG TEST SYSTEMS GmbH & Co. KG Vorrichtung zum prüfen von leiterplatten
US6233184B1 (en) 1998-11-13 2001-05-15 International Business Machines Corporation Structures for wafer level test and burn-in
JP4234244B2 (ja) 1998-12-28 2009-03-04 富士通マイクロエレクトロニクス株式会社 ウエハーレベルパッケージ及びウエハーレベルパッケージを用いた半導体装置の製造方法
KR100355225B1 (ko) * 1999-07-12 2002-10-11 삼성전자 주식회사 교류 스트레스의 번-인 테스트가 가능한 집적회로 및 이를 이용한 테스트 방법
US6337576B1 (en) 1999-07-19 2002-01-08 Alpine Microsystems, Inc. Wafer-level burn-in
DE19936321C2 (de) * 1999-08-02 2003-12-24 Infineon Technologies Ag Anordnung und Verfahren zum Testen einer Vielzahl von Halbleiterchips auf Waferebene
US6603323B1 (en) * 2000-07-10 2003-08-05 Formfactor, Inc. Closed-grid bus architecture for wafer interconnect structure
JP2002033363A (ja) * 2000-07-19 2002-01-31 Hitachi Ltd 半導体ウエハ、半導体チップ、および半導体装置の製造方法
JP4149377B2 (ja) 2001-06-07 2008-09-10 株式会社ルネサステクノロジ 半導体装置の製造方法
KR100575882B1 (ko) * 2003-11-26 2006-05-03 주식회사 하이닉스반도체 번인 테스트용 내부 전압 발생 장치
US8513970B2 (en) 2008-12-26 2013-08-20 Nec Corporation Semiconductor device and method of testing the same
WO2010107490A1 (en) 2009-03-18 2010-09-23 Touchtunes Music Corporation Entertainment server and associated social networking services
US8274301B2 (en) * 2009-11-02 2012-09-25 International Business Machines Corporation On-chip accelerated failure indicator
WO2011094330A1 (en) 2010-01-26 2011-08-04 Touchtunes Music Corporation Digital jukebox device with improved user interfaces, and associated methods
DE112014003371T5 (de) * 2013-07-22 2016-04-07 Murata Manufacturing Co., Ltd. Oberflächenemitter-array
CN112907655B (zh) * 2021-02-08 2021-12-17 深圳信息职业技术学院 Ic烧录的定位方法、系统、终端设备及计算机存储介质

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3781683A (en) * 1971-03-30 1973-12-25 Ibm Test circuit configuration for integrated semiconductor circuits and a test system containing said configuration
US3890611A (en) * 1972-01-24 1975-06-17 Analog Devices Inc Constant-current digital-to-analog converter
US3849872A (en) * 1972-10-24 1974-11-26 Ibm Contacting integrated circuit chip terminal through the wafer kerf
US4038648A (en) * 1974-06-03 1977-07-26 Chesley Gilman D Self-configurable circuit structure for achieving wafer scale integration
GB1487945A (en) * 1974-11-20 1977-10-05 Ibm Semiconductor integrated circuit devices
US4281449A (en) * 1979-12-21 1981-08-04 Harris Corporation Method for qualifying biased burn-in integrated circuits on a wafer level
US4467400A (en) * 1981-01-16 1984-08-21 Burroughs Corporation Wafer scale integrated circuit
US4479088A (en) * 1981-01-16 1984-10-23 Burroughs Corporation Wafer including test lead connected to ground for testing networks thereon
US4413271A (en) * 1981-03-30 1983-11-01 Sprague Electric Company Integrated circuit including test portion and method for making
EP0072690A3 (en) * 1981-08-17 1983-11-09 Fujitsu Limited A mis device and a method of manufacturing it
JPS5911661A (ja) * 1982-07-13 1984-01-21 Nec Corp 集積回路
JPS59172243A (ja) * 1983-03-18 1984-09-28 Nippon Denso Co Ltd Ｉｃウエハ
DE3481958D1 (de) * 1983-05-24 1990-05-17 Toshiba Kawasaki Kk Integrierte halbleiterschaltungsanordnung.
DE3483137D1 (de) * 1983-11-30 1990-10-11 Fujitsu Ltd Ec-torfeld.
JPS60140842A (ja) * 1983-12-28 1985-07-25 Nec Corp 半導体装置
JPH0714002B2 (ja) * 1984-05-15 1995-02-15 セイコーエプソン株式会社 チップへの信号供給方法
EP0170052B1 (en) * 1984-07-02 1992-04-01 Fujitsu Limited Master slice type semiconductor circuit device
SU1250997A1 (ru) * 1984-10-01 1986-08-15 Предприятие П/Я Р-6668 Способ контрол интегральных микросхем
US4721495A (en) * 1985-09-01 1988-01-26 Nippon Seiko Kabushiki Kaisha Autotensioner
JPS6295853A (ja) * 1985-10-22 1987-05-02 Nec Corp 半導体集積回路
US4813017A (en) * 1985-10-28 1989-03-14 International Business Machines Corportion Semiconductor memory device and array
JPH0740583B2 (ja) * 1986-03-24 1995-05-01 日立コンピユ−タエンジニアリング株式会社 半導体装置の試験方法及びその実施用ウエハ
JPS6343344A (ja) * 1986-08-08 1988-02-24 Nec Corp マスタスライス方式ｌｓｉのブロツク
JPS63213965A (ja) * 1987-03-03 1988-09-06 Mitsubishi Electric Corp 半導体装置
US4910574A (en) * 1987-04-30 1990-03-20 Ibm Corporation Porous circuit macro for semiconductor integrated circuits
JPS63300530A (ja) * 1987-05-29 1988-12-07 Nec Corp 集積回路
JP2606845B2 (ja) * 1987-06-19 1997-05-07 富士通株式会社 半導体集積回路
JPS6435934A (en) * 1987-07-30 1989-02-07 Hitachi Ltd Semiconductor integrated circuit device
US4812742A (en) * 1987-12-03 1989-03-14 Unisys Corporation Integrated circuit package having a removable test region for testing for shorts and opens
JPH01239950A (ja) * 1988-03-22 1989-09-25 Mitsubishi Electric Corp 半導体ウエハ
JPH01298733A (ja) * 1988-05-27 1989-12-01 Fujitsu Ltd 自走機能内蔵集積回路
US5014110A (en) * 1988-06-03 1991-05-07 Mitsubishi Denki Kabushiki Kaisha Wiring structures for semiconductor memory device
JPH0227467A (ja) * 1988-07-16 1990-01-30 Fuji Electric Co Ltd 演算装置間の同期方法
JP2746925B2 (ja) * 1988-08-04 1998-05-06 株式会社リコー 画像形成装置
JPH039364A (ja) * 1989-06-06 1991-01-17 Toshiba Corp 電子写真感光体
JP2508288B2 (ja) * 1989-08-30 1996-06-19 三菱電機株式会社 半導体記憶装置
JPH03106029A (ja) * 1989-09-20 1991-05-02 Fujitsu Ltd ウエハ・スケール・ｉｃ
US5070296A (en) * 1990-06-22 1991-12-03 Honeywell Inc. Integrated circuit interconnections testing
US5059899A (en) * 1990-08-16 1991-10-22 Micron Technology, Inc. Semiconductor dies and wafers and methods for making

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US5294776A (en) 1994-03-15
US5138427A (en) 1992-08-11
DE69030283T2 (de) 1997-08-07
EP0405586A1 (en) 1991-01-02
JP2585799B2 (ja) 1997-02-26
JPH0334555A (ja) 1991-02-14
DE69030283D1 (de) 1997-04-30
KR940006577B1 (ko) 1994-07-22
EP0405586B1 (en) 1997-03-26

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