KR910019236A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR910019236A
KR910019236A KR1019910006532A KR910006532A KR910019236A KR 910019236 A KR910019236 A KR 910019236A KR 1019910006532 A KR1019910006532 A KR 1019910006532A KR 910006532 A KR910006532 A KR 910006532A KR 910019236 A KR910019236 A KR 910019236A
Authority
KR
South Korea
Prior art keywords
semiconductor device
pads
chips
bonding pad
wafer
Prior art date
Application number
KR1019910006532A
Other languages
English (en)
Other versions
KR960004460B1 (ko
Inventor
도루 후루야마
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910019236A publication Critical patent/KR910019236A/ko
Application granted granted Critical
Publication of KR960004460B1 publication Critical patent/KR960004460B1/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명의 제 1 실시예에 따른 DRAM의 일부를 나타낸 회로도, 제 2 도는 본 발명의 제 2 실시예에 따른 DRAM의 일부를 나타낸 회로도, 제 5 도는 내지 제 7 도는 각각 본 발명의 제 3 실시예 내지 제 7 실시예에 따른 DRAM의 일부를나타낸 회로도이다.

Claims (7)

  1. 전원이외의 임의의 신호단자에 대해서 복수개의 본딩패드가 설치되어 있는 것을 특징으로 하는 반도체 장치.
  2. 제 1 항에 있어서, 상기 복수개의 본딩패드중 제 1 패드(11)와 제 2 패드(12)는 직접 접속되지 않고, 상기 제 1 패드(11)에 접속되는 제 1 입력회로(21,51,61,71) 및 상기 제2패드 (12)에 접속되는 제2입력회로(22, 52, 62, 72)와상기 제1입력회로(21, 51, 61, 71)의 출력 및 상기 제 2 입력회로(22,52,62,72)의 출력이 입력되는 제 3 회로(23,53,63,73,74)를 구비한 것을 특징으로 하는 반도체장치.
  3. 제 1 항 또는 제 2 항에 있어서, 상기 복수개의 본딩패드중 적어도 1 개는 어셈블리시에 사용되지 않는 보조본딩 패드인 것을 특징으로 하는 반도체 장치.
  4. 제 3 항에 있어서, 상기 보조본딩패드는 어셀블리시에 사용되는 본딩패드보다도 크게 형성되어 있는 것을 특징으로 하는 반도체장치.
  5. 제 3 항에 있어서, 상기 보조본딩패드는 반도체장치가 웨이퍼상태인 때에 복수의 칩에서 공유하는 것을 특징으로 하는 반도체장치.
  6. 제 5 항에 있어서, 상기 복수칩은 웨이퍼패턴노광장치에 의해 일괄적으로 노광되는 칩인 것을 특징을 하는 반도체장치.
  7. 제 5 항에 있어서, 상기 복수칩은 웨이퍼상의 모든 칩인 것을 특징으로 하는 반도체장치.
    ※ 참고사항 : 최초출원내용에 의하여 공개하는 것임.
KR1019910006532A 1990-04-25 1991-04-24 반도체장치 KR960004460B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2107542A JP2531827B2 (ja) 1990-04-25 1990-04-25 半導体装置及びその製造方法
JP02-107542 1990-04-25

Publications (2)

Publication Number Publication Date
KR910019236A true KR910019236A (ko) 1991-11-30
KR960004460B1 KR960004460B1 (ko) 1996-04-06

Family

ID=14461831

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910006532A KR960004460B1 (ko) 1990-04-25 1991-04-24 반도체장치

Country Status (4)

Country Link
US (1) US5386127A (ko)
EP (1) EP0454134A3 (ko)
JP (1) JP2531827B2 (ko)
KR (1) KR960004460B1 (ko)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100200916B1 (ko) * 1995-11-16 1999-06-15 윤종용 웨이퍼 테스트 신호 발생기를 가지는 반도체 메모리 장치
JP3019918B2 (ja) * 1996-08-12 2000-03-15 日本電気株式会社 半導体集積回路及びその電源供給回路
US6356958B1 (en) 1999-02-08 2002-03-12 Mou-Shiung Lin Integrated circuit module has common function known good integrated circuit die with multiple selectable functions
US6180426B1 (en) 1999-03-01 2001-01-30 Mou-Shiung Lin High performance sub-system design and assembly
JP2001358293A (ja) * 2000-06-12 2001-12-26 Toshiba Corp 半導体装置
JP5085829B2 (ja) * 2002-05-07 2012-11-28 メギカ・コーポレイション 集積回路チップ構造
JP2006324359A (ja) * 2005-05-17 2006-11-30 Elpida Memory Inc 半導体チップ及び半導体装置
KR100734290B1 (ko) 2005-11-28 2007-07-02 삼성전자주식회사 출력 채널이 공유되는 테스트 패드를 구비하는 필름형반도체 패키지 및 필름형 반도체 패키지의 테스트 방법,테스트 채널이 공유되는 패턴을 구비하는 테스트 장치 및반도체 장치 그리고 반도체 장치에서의 테스트 방법
WO2011089849A1 (en) * 2010-01-20 2011-07-28 Semiconductor Energy Laboratory Co., Ltd. Portable electronic device
JP2012114241A (ja) * 2010-11-25 2012-06-14 Renesas Electronics Corp 半導体チップおよび半導体装置
JP5822370B2 (ja) * 2011-07-05 2015-11-24 インテル・コーポレーション セルフディセーブルチップイネーブル入力
CN104113355B (zh) 2013-04-19 2017-01-11 联发科技（新加坡）私人有限公司 一种电子装置
JP7426702B2 (ja) * 2020-02-13 2024-02-02 ザインエレクトロニクス株式会社 半導体装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4413271A (en) * 1981-03-30 1983-11-01 Sprague Electric Company Integrated circuit including test portion and method for making
JPS59188956A (ja) * 1983-04-11 1984-10-26 Nec Corp 半導体装置
JPH0714002B2 (ja) * 1984-05-15 1995-02-15 セイコーエプソン株式会社 チップへの信号供給方法
JPS61222148A (ja) * 1985-03-08 1986-10-02 Fujitsu Ltd １チツプマイクロコンピユ−タの製造方法
JPS61253847A (ja) * 1985-05-02 1986-11-11 Nec Corp 高信頼度を有する半導体装置
JP2605687B2 (ja) * 1986-04-17 1997-04-30 三菱電機株式会社 半導体装置
JPS62271443A (ja) * 1986-05-20 1987-11-25 Toshiba Corp 半導体装置
US4884122A (en) * 1988-08-05 1989-11-28 General Electric Company Method and configuration for testing electronic circuits and integrated circuit chips using a removable overlay layer
JPS63128729A (ja) * 1986-11-19 1988-06-01 Nec Corp 半導体ウエハ−プロ−バ−用ステ−ジ
JPS63128729U (ko) * 1987-02-14 1988-08-23
JP2795846B2 (ja) * 1987-11-25 1998-09-10 株式会社東芝 半導体装置
JP2594988B2 (ja) * 1987-11-27 1997-03-26 株式会社日立製作所 半導体集積回路装置の動作電位供給配線の配線設計方法
US5008727A (en) * 1988-01-22 1991-04-16 Matsushita Electric Industrial Co., Ltd. Standard cell having test pad for probing and semiconductor integrated circuit device containing the standard cells
JPH01278033A (ja) * 1988-04-28 1989-11-08 Nec Corp 半導体集積回路のパッド配置構造
JP2560805B2 (ja) * 1988-10-06 1996-12-04 三菱電機株式会社 半導体装置

Also Published As

Publication number Publication date
KR960004460B1 (ko) 1996-04-06
US5386127A (en) 1995-01-31
EP0454134A2 (en) 1991-10-30
JP2531827B2 (ja) 1996-09-04
EP0454134A3 (en) 1993-05-19
JPH047853A (ja) 1992-01-13

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