KR890017794A - 마스터-슬라이스형 반도체집적회로 - Google Patents

마스터-슬라이스형 반도체집적회로 Download PDF

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Publication number
KR890017794A
KR890017794A KR1019890006518A KR890006518A KR890017794A KR 890017794 A KR890017794 A KR 890017794A KR 1019890006518 A KR1019890006518 A KR 1019890006518A KR 890006518 A KR890006518 A KR 890006518A KR 890017794 A KR890017794 A KR 890017794A
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KR
South Korea
Prior art keywords
integrated circuit
semiconductor integrated
pads
master
input
Prior art date
Application number
KR1019890006518A
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English (en)
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KR960006977B1 (ko
Inventor
야스노리 다나카
테루오 고바야시
마사히로 이시바시
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로 일렉트릭스 가부시키가이샤
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Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로 일렉트릭스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR890017794A publication Critical patent/KR890017794A/ko
Application granted granted Critical
Publication of KR960006977B1 publication Critical patent/KR960006977B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1735—Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • C—CHEMISTRY; METALLURGY
    • C21—METALLURGY OF IRON
    • C21B—MANUFACTURE OF IRON OR STEEL
    • C21B13/00—Making spongy iron or liquid steel, by direct processes
    • C21B13/12—Making spongy iron or liquid steel, by direct processes in electric furnaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음

Description

마스터-슬라이스형 반도체집적회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명에 따른 마스터-슬라이스형 반도체집적회로의 1실시예에 따른 칩레이아웃을 도시한 도면, 제 2 도는 상기 실시예에 따른 집적회로의 주변부를 발췌하여 도시한 도면, 제 3 도는 제 2 도에 도시된 회로에 배선패턴을 형성한 다음의 상태를 도시한 도면.

Claims (2)

  1. 복수개의 패드(14)와, 구동능력이 각각 같도록 되어있으면서 상기 각 패트(14)에 대해 n개(n은 2이상의 정수)씩 설치되는 버퍼를 갖춘 입출력셀(13)을 구비하여 구성되어, 상기 패드(14)에 배치간격에 따라 패드 1개당 입출력셀의 수 n을 설정하도록 된 것을 특징으로 하는 마스터-슬라이스형 반도체집적회로.
  2. 복수개의 패드(14)와, 구동능력이 각각 같도록 되어 있으면서 상기 패트의 m배(m은 2이상의 정수)의 수만큼 설치된 버퍼를 갖춘 입출력셀(13)을 구비하여 구성된 것을 특징으로 하는 마스터-슬라이스형 반도체집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890006518A 1988-05-16 1989-05-16 마스터-슬라이스형 반도체집적회로 KR960006977B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP88-118765 1988-05-16
JP63-118765 1988-05-16
JP63118765A JPH01289138A (ja) 1988-05-16 1988-05-16 マスタースライス型半導体集積回路

Publications (2)

Publication Number Publication Date
KR890017794A true KR890017794A (ko) 1989-12-18
KR960006977B1 KR960006977B1 (ko) 1996-05-25

Family

ID=14744510

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890006518A KR960006977B1 (ko) 1988-05-16 1989-05-16 마스터-슬라이스형 반도체집적회로

Country Status (5)

Country Link
US (1) US4942317A (ko)
EP (1) EP0342590B1 (ko)
JP (1) JPH01289138A (ko)
KR (1) KR960006977B1 (ko)
DE (1) DE68917515T2 (ko)

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US6825698B2 (en) * 2001-08-29 2004-11-30 Altera Corporation Programmable high speed I/O interface
JP2509696B2 (ja) * 1989-04-26 1996-06-26 株式会社東芝 ゲ―トアレ―半導体集積回路装置
JPH03274765A (ja) * 1990-03-23 1991-12-05 Mitsubishi Electric Corp マスタスライス方式半導体装置
US5208764A (en) * 1990-10-29 1993-05-04 Sun Microsystems, Inc. Method for optimizing automatic place and route layout for full scan circuits
JP2720629B2 (ja) * 1991-04-26 1998-03-04 日本電気株式会社 集積回路のレイアウトシステム
WO1993012540A1 (en) * 1991-12-10 1993-06-24 Vlsi Technology, Inc. Integrated circuit with variable pad pitch
KR960003042B1 (ko) * 1992-05-26 1996-03-04 가부시끼가이샤 도시바 데이타 출력 장치
US5535084A (en) * 1992-07-24 1996-07-09 Kawasaki Steel Corporation Semiconductor integrated circuit having protection circuits
JPH06326194A (ja) * 1993-05-17 1994-11-25 Mitsubishi Electric Corp 半導体集積回路装置
US5469473A (en) * 1994-04-15 1995-11-21 Texas Instruments Incorporated Transceiver circuit with transition detection
US6480817B1 (en) * 1994-09-01 2002-11-12 Hynix Semiconductor, Inc. Integrated circuit I/O pad cell modeling
EP0743756B1 (de) * 1995-05-05 1997-08-13 Siemens Aktiengesellschaft Konfigurierbare integrierte Schaltung
US5995740A (en) * 1996-12-23 1999-11-30 Lsi Logic Corporation Method for capturing ASIC I/O pin data for tester compatibility analysis
US6157051A (en) * 1998-07-10 2000-12-05 Hilevel Technology, Inc. Multiple function array based application specific integrated circuit
JP2002026130A (ja) * 2000-07-06 2002-01-25 Nec Microsystems Ltd 半導体集積回路及びｉ／ｏブロック配置方法
US7281227B2 (en) * 2004-09-30 2007-10-09 Infineon Technologies Ag Method and device for the computer-aided design of a supply network
US8302060B2 (en) * 2010-11-17 2012-10-30 Taiwan Semiconductor Manufacturing Co., Ltd. I/O cell architecture
WO2020073901A1 (en) * 2018-10-11 2020-04-16 Changxin Memory Technologies, Inc. Semiconductor structure, memory device, semiconductor device and method of manufacturing the same

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Publication number Priority date Publication date Assignee Title
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
JPS5835963A (ja) * 1981-08-28 1983-03-02 Fujitsu Ltd 集積回路装置
EP0074805B2 (en) * 1981-09-10 1992-03-11 Fujitsu Limited Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers
JPS593950A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd ゲ−トアレイチツプ
JPS6027145A (ja) * 1983-07-25 1985-02-12 Hitachi Ltd 半導体集積回路装置
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Also Published As

Publication number Publication date
KR960006977B1 (ko) 1996-05-25
EP0342590A2 (en) 1989-11-23
US4942317A (en) 1990-07-17
DE68917515D1 (de) 1994-09-22
EP0342590B1 (en) 1994-08-17
DE68917515T2 (de) 1995-02-09
JPH01289138A (ja) 1989-11-21
EP0342590A3 (en) 1991-09-04

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