KR900013616A - 집적회로의 배치배선방식 - Google Patents

집적회로의 배치배선방식 Download PDF

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Publication number
KR900013616A
KR900013616A KR1019900001521A KR900001521A KR900013616A KR 900013616 A KR900013616 A KR 900013616A KR 1019900001521 A KR1019900001521 A KR 1019900001521A KR 900001521 A KR900001521 A KR 900001521A KR 900013616 A KR900013616 A KR 900013616A
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KR
South Korea
Prior art keywords
buffers
integrated circuit
wiring
clock
buffer
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KR1019900001521A
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English (en)
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KR930008646B1 (ko
Inventor
히로유키 와타나베
치카히로 호리
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR900013616A publication Critical patent/KR900013616A/ko
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Publication of KR930008646B1 publication Critical patent/KR930008646B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

내용 없음

Description

집적회로의 배치배선방식
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1도는 본 발명에 따른 집적회로의 배치배선방식의 기본원리도,
제 2도는 본 발명에 따른 집접회로의 배치방식에 있어서 2단째 각 버퍼를 논리회로영역의 두변 주위에 배치한 실시예를 나타낸 도면.
제 3도는 2단째의 각 버퍼를 논리회로영역의 세변 주위에 배치한 실시예를 나타낸 도면.
제 4도는 2단째의 각 버퍼를 논리 회로영역의 네변 주위에 배치한 실시예를 나타낸 도면.

Claims (7)

  1. 클럭신호입력용 패드부(1)와, 입력측이 이 클럭신호입력용 패드부(1)에 접속된 초단버퍼(2-1) 및, 이 초단버퍼(2-1)에서 발생된 출력에 의해 구동되는 2단째의 복수(複數)의 버퍼로 이루어진 클럭공급회로 (3-1,3-2,3-3)와 이 클럭공급회로(3-1,3-2,3-3)로부터 클럭신호가 공급되는 논리회로 영역(4)을 구비한 집적회로에 있어서, 적어도 상기 초단버퍼(2-1) 및 2단째의 각 버퍼(3-1,3-2,3-3)와 그 사이를 연결하는 배선이 상기 논리회로영역(4)에 인접하여 그 주변에 배치배선된 것을 특징으로 하는 집적회로의 배치배선방식.
  2. 제1항에있어서, 상기 논리회로영역(4)의 주변에 배치된 버퍼(2-1,3-2,3-2...)가 전원배선(92)아래에 배치된 것을 특징으로 하는 집적회로의 배치배선방식.
  3. 제 1항에 있어서, 상기 논리회로영역(4)의 전원선(101) 및 상기 논리회로영역(4)의 주변에 배치된 복수의 상기 버퍼(2-1,3-1,3-2.....)의 전원선(102)이 집적회로의 기판(5′)상에서 분리되어 있는 것을 특징으로 하는 집적회로의 배치배선방식.
  4. 제 1항에 있어서, 상기 2단째의 각 버퍼(3-1,3-2,3-3....)에 접속된 부하용량이 각각 다를 경우, 유사부하용량(8;類似負荷容量)을 조정함으로써 부하용량을 동일하게 하는 것을 특징으로 하는 집적회로의 배치배선방식.
  5. 상기 제 1항에 있어서 상기 2단째의 각 버퍼(3-1,3-2,3-3,...)의 구동능력을 전부 동일하게 하고, 이 2단째의 각 버퍼(3-1,3-2,3-3,...)의 출력측 클럭배선을 그것에 접속된 부하의 크기에 맞도록 우회시킴으로써 클럭의 시간오차를 방지하도록 된 것을 특징으로 하는 집적회로의 배치배선방식.
  6. 제 1항에 있어서, 상기 2단째의 각 버퍼(3-1,3-2,3-2,....)를 구성하는 MOS트랜지스터의 게이트 길이가 다른 MOS트랜지스터의 게이트 길이보다 길게 형성되어 있는 것을 특징으로 하는 집적회로의 배치배선방식.
  7. 제 1항에 있어서, 상기 초단버퍼로부터 2단째의 각 버퍼까지의 배선길이가 동일한 것을 특징으로 하는 집적회로의 배치배선방식.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900001521A 1989-02-08 1990-02-07 집적회로의 배치배선방식 KR930008646B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP89-29190 1989-02-08
JP01-29190 1989-02-08
JP1029190A JPH0824143B2 (ja) 1989-02-08 1989-02-08 集積回路の配置配線方式

Publications (2)

Publication Number Publication Date
KR900013616A true KR900013616A (ko) 1990-09-06
KR930008646B1 KR930008646B1 (ko) 1993-09-11

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KR1019900001521A KR930008646B1 (ko) 1989-02-08 1990-02-07 집적회로의 배치배선방식

Country Status (3)

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US (1) US5172330A (ko)
JP (1) JPH0824143B2 (ko)
KR (1) KR930008646B1 (ko)

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Also Published As

Publication number Publication date
KR930008646B1 (ko) 1993-09-11
US5172330A (en) 1992-12-15
JPH02208956A (ja) 1990-08-20
JPH0824143B2 (ja) 1996-03-06

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