KR950034768A - 반도체 집적회로장치 - Google Patents
반도체 집적회로장치 Download PDFInfo
- Publication number
- KR950034768A KR950034768A KR1019950003818A KR19950003818A KR950034768A KR 950034768 A KR950034768 A KR 950034768A KR 1019950003818 A KR1019950003818 A KR 1019950003818A KR 19950003818 A KR19950003818 A KR 19950003818A KR 950034768 A KR950034768 A KR 950034768A
- Authority
- KR
- South Korea
- Prior art keywords
- pads
- mos transistors
- integrated circuit
- semiconductor integrated
- circuit device
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 101100123053 Arabidopsis thaliana GSH1 gene Proteins 0.000 claims abstract 4
- 101100298888 Arabidopsis thaliana PAD2 gene Proteins 0.000 claims abstract 4
- 101000590281 Homo sapiens 26S proteasome non-ATPase regulatory subunit 14 Proteins 0.000 claims abstract 4
- 101001114059 Homo sapiens Protein-arginine deiminase type-1 Proteins 0.000 claims abstract 4
- 101150092599 Padi2 gene Proteins 0.000 claims abstract 4
- 102100023222 Protein-arginine deiminase type-1 Human genes 0.000 claims abstract 4
- 102100035735 Protein-arginine deiminase type-2 Human genes 0.000 claims abstract 4
- 101100272964 Arabidopsis thaliana CYP71B15 gene Proteins 0.000 claims abstract 3
- 101150030164 PADI3 gene Proteins 0.000 claims abstract 3
- 102100035734 Protein-arginine deiminase type-3 Human genes 0.000 claims abstract 3
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11898—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
1. 청구범위에 기재된 발명이 속한 기술분야
본 발명은 반도체 메모리등의 반도체 집적 회로 장치에 관한 것이다.
2. 발명이 해결하려고 하는 과제
입출력 회로의 패드와 트랜지스터의 배치 구조를 연구함에 따라 칩 전체를 소형화한 반도체 집적회로 장치를 실현한다.
3. 발명의 해결방법의 요지
장면 Y와 단면 X를 갖는 반도체 칩(1)의 단면 X를 다른 단부 영역에 패드 PAD와 그 패드에 접속되는 P채널 MOS 트랜지스터와 N 채널 MOS 트랜지스터로 이루어지는 조를 복수로 배치하여 되는 반도체 집적회로 장치에 있어서, 복수의 패트 PAD1, PAD2, PAD3을 상기 단면 X를 따라 배열함과 동시에, 그들의 패드와 조를 이루는 MOS 트랜지스터 P1,N1,P2,N2,P3,N3을 패드보다도 칩 내측의 영역에 설치한 것을 특징으로 한다.
4. 발명의 중요한 용도
반도체 집적회로장치의 단변 방향 사이즈를 작게할 수 있고 그것에 따라 전체의 사이즈를 소형화 할 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명을 실시한 반도체 메모리의 요부의 레이아우트 패턴을 나타내는 도면, 제2도는 본 발명의 다른 실시예에 대하여 요부의 레이아우트패턴을 나타내는 도면, 제3도는 본 발명에 의하여 칩사이즈가 작아지는 효과를 설명하기 위한 도면.
Claims (3)
- 장변 Y와 단변 X를 갖는 반도체 칩(1)의 단변 X를 따른 단부영역에 패드 PAD와 그 패드에 접속되는 P채널 MOS 트랜지스터와 N 채널 MOS 트랜지스터로 이루어지는 조를 복수로 배치하여 되는 반도체 집적회로장치에 있어서, 복수의 패트 PAD1,PAD2,PAD3을 상기 단면 X를 따라 배열함과 동시에, 그들의 패드와 조를 이루는 MOS 트랜지스터 P1,N1,P2,N2,P3,N3을 패드보다도 칩 내측의 영역에 설치한 것을 특징으로 하는 반도체 집적회로장치.
- 장벼녀 Y와 단변 X을 갖는 반도체 칩(1)의 단변 X를 따른 단부영역에 패드 PAD와 그 패드에 접속되는 P 채널 MOS 트랜지스터와 N 채널 MOS 트랜지스터로 이루어지는 조를 복수로 배치하여 되는 반도체 집적회로장치에 있어서, 복수의 패드 PAD1,PAD2,PAD3을 상기 단면 X를 따라 배열함과 동시에, 그들의 패드와 조를 이루는 MOS 트랜지스터 P1,N1,P2,N2,P3,N3의 한쪽을 상기 패드보다도 칩 내측의 영역에 배열하고, 다른쪽의 MOS 트랜지스터를 상기 패드보다도 칩 외측의 영역에 배열한 것을 특징으로 하는 반도체 집적회로장치.
- 장변 Y와 단변 X를 갖는 반도체 칩(1)의 단변 X를 따른 단부영역에 패드 PAD와 그 패드에 접속되는 P채널 MOS트랜지스터와 N 채널 MOS트랜지스터로 이루어지는 조를 복수로 배치하여 되는 반도체 집적회로장치에 있어서, 가상의 장방형의 하나의 대각위에 제1, 제2패드 PAD1,PAD2 설치되고, 다른 대각위에 상기 패드와 조를 이루는 두개의 N채널 MOS 트랜지스터 N1,N2와 두개의 P채널 MOS 트랜지스터 P1,P2 쌍이 각각 설치되어 있는 것을 특징으로 하는, 반도체 집적회로 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP94-58425 | 1994-03-29 | ||
JP05842594A JP3181000B2 (ja) | 1994-03-29 | 1994-03-29 | 半導体集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950034768A true KR950034768A (ko) | 1995-12-28 |
KR100310116B1 KR100310116B1 (ko) | 2001-12-17 |
Family
ID=13084036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019950003818A KR100310116B1 (ko) | 1994-03-29 | 1995-02-27 | 반도체집적회로장치 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5543651A (ko) |
JP (1) | JP3181000B2 (ko) |
KR (1) | KR100310116B1 (ko) |
TW (1) | TW370721B (ko) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1993012540A1 (en) * | 1991-12-10 | 1993-06-24 | Vlsi Technology, Inc. | Integrated circuit with variable pad pitch |
JPH09107048A (ja) * | 1995-03-30 | 1997-04-22 | Mitsubishi Electric Corp | 半導体パッケージ |
JP4313544B2 (ja) * | 2002-05-15 | 2009-08-12 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路 |
US6858945B2 (en) * | 2002-08-21 | 2005-02-22 | Broadcom Corporation | Multi-concentric pad arrangements for integrated circuit pads |
DE10331570B4 (de) * | 2003-07-11 | 2005-09-22 | Infineon Technologies Ag | Halbleiterchip |
JP5082527B2 (ja) * | 2005-11-25 | 2012-11-28 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
JP5082309B2 (ja) * | 2005-11-25 | 2012-11-28 | セイコーエプソン株式会社 | 集積回路装置及び電子機器 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5162893A (en) * | 1988-05-23 | 1992-11-10 | Fujitsu Limited | Semiconductor integrated circuit device with an enlarged internal logic circuit area |
JPH0529457A (ja) * | 1991-07-24 | 1993-02-05 | Mitsubishi Electric Corp | 半導体集積回路 |
-
1994
- 1994-03-29 JP JP05842594A patent/JP3181000B2/ja not_active Expired - Fee Related
-
1995
- 1995-02-27 KR KR1019950003818A patent/KR100310116B1/ko not_active IP Right Cessation
- 1995-03-28 US US08/413,219 patent/US5543651A/en not_active Expired - Lifetime
- 1995-04-07 TW TW084103298A patent/TW370721B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TW370721B (en) | 1999-09-21 |
JPH07273209A (ja) | 1995-10-20 |
US5543651A (en) | 1996-08-06 |
KR100310116B1 (ko) | 2001-12-17 |
JP3181000B2 (ja) | 2001-07-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR900013616A (ko) | 집적회로의 배치배선방식 | |
KR850005059A (ko) | 스위칭 잡음을 감소시킨 lsi 게이트 어레이 | |
KR910003940A (ko) | 반도체집적회로 | |
KR910019343A (ko) | 입력회로 | |
KR930007096A (ko) | 인체 효과를 감소시키기 위한 엔-채널 풀업 트랜지스터 | |
KR910002130A (ko) | 반도체집적회로 | |
KR940010418B1 (ko) | 어드레스디코드회로 | |
KR950034768A (ko) | 반도체 집적회로장치 | |
KR920007194A (ko) | 표준 셀 방식의 반도체 집접회로 | |
KR930006875A (ko) | 집적회로 | |
KR910016005A (ko) | 반도체 집적회로 | |
KR970024017A (ko) | 반도체장치 | |
KR900013655A (ko) | 반도체 회로 | |
KR970030788A (ko) | Cmos 반도체 장치 | |
KR910017424A (ko) | 반도체 집적회로 장치의 메모리셀 회로 | |
KR950024063A (ko) | 전 가산기 | |
KR900019198A (ko) | 반도체 집적회로장치 | |
KR940000256Y1 (ko) | 반가산기 회로 | |
JPH0446416A (ja) | 2つの入力と1つの出力を備えた論理回路 | |
KR930011286A (ko) | 베이스 어레이 | |
KR100234411B1 (ko) | Rs 래치회로 | |
KR890006531Y1 (ko) | 논리소자 집적회로 | |
KR970055483A (ko) | Rs 래치 회로 | |
KR970055375A (ko) | 게이트 수를 최소화한 플립-플롭 | |
KR930003365A (ko) | 반도체 집적회로 장치 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20090910 Year of fee payment: 9 |
|
LAPS | Lapse due to unpaid annual fee |