KR910003940A - 반도체집적회로 - Google Patents
반도체집적회로 Download PDFInfo
- Publication number
- KR910003940A KR910003940A KR1019900011308A KR900011308A KR910003940A KR 910003940 A KR910003940 A KR 910003940A KR 1019900011308 A KR1019900011308 A KR 1019900011308A KR 900011308 A KR900011308 A KR 900011308A KR 910003940 A KR910003940 A KR 910003940A
- Authority
- KR
- South Korea
- Prior art keywords
- mos transistor
- integrated circuit
- semiconductor integrated
- channel
- driving
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 반도체집적회로의 1실시예를 나타내는 회로도,
제2도는 본 발명의 다른 실시예를 나타내는 회로도,
제3도는 본 발명에 따른 또 다른 실시예를 나타내는 회로도.
Claims (6)
- 외부신호입력단자에 게이트전극이 접속된 N채널형 제1구동용 MOS트랜지스터 (N2')를 입력회로의 일부로서 갖춘 반도체집적회로에 있어서, 상기 제1구동용 MOS트랜지스터(N2')의 임계전압이 해당 직접회로의 다른 내부회로를 구성하는 제2구동용 N채널 MOS트랜지스터(N1,N3)의 임계전압보다도 낮게 설정된 것을 특징으로 하는 반도체집적회로.
- 제1항에 있어서, 상기 제1구동용MOS트랜지스터(N2')의 임계전압이 거의 OV이하로 설정된 것을 특징으로 하는 반도체집적회로.
- 제1항 또는 제2항에 있어서, 상기 입력회로에는 P채널형 제1MOS트랜지스터 (P2)가 더 구비되고, 상기 제1구동용 MOS트랜지스터(N2)의 게이트전극과 상기 P채널형 제1MOS트랜지스터(P2)의 게이트 전극이 공통 접속된 실질적인 반전회로가 상기 제1구동용 MOS트랜지스터와 상기 P채널형 제1MOS트랜지스터로 구성된 것을 특징으로 하는 반도체집적회로
- 제1항 또는 제2항에 있어서, 상기 제1구동용 MOS트랜지스터(N2')의 부하로서 게이트와 소오스가 공통 접속된 디플리이선형 MOS트랜지스터(P2')가 더 구비된 것을 특징으로 하는 반도체집적회로.
- 제3항에 있어서, 상기 제1구동용 MOS트랜지스터와 상기 P채널형 제1MOS트랜지스터가 노아 게이트의 일부를 구성하도록 된 것을 특징으로 하는 반도체집적회로.
- 제3항에 있어서, 상기 제1구동용 MOS트랜지스터와 상기 P채널형 제1MOS트랜지스터가 낸드게이트의 일부를 구성하도록 된 것을 특징으로 하는 반도체집적회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1195951A JPH07114359B2 (ja) | 1989-07-28 | 1989-07-28 | 半導体集積回路 |
JP89-195951 | 1989-07-28 | ||
JP01-195951 | 1989-07-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910003940A true KR910003940A (ko) | 1991-02-28 |
KR930003926B1 KR930003926B1 (ko) | 1993-05-15 |
Family
ID=16349690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900011308A KR930003926B1 (ko) | 1989-07-28 | 1990-07-25 | 반도체집적회로 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5073726A (ko) |
EP (1) | EP0410473B1 (ko) |
JP (1) | JPH07114359B2 (ko) |
KR (1) | KR930003926B1 (ko) |
DE (1) | DE69023565T2 (ko) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04120817A (ja) * | 1990-09-11 | 1992-04-21 | Mitsubishi Electric Corp | Lsi回路の出力バッファ回路 |
US5200921A (en) * | 1990-09-20 | 1993-04-06 | Fujitsu Limited | Semiconductor integrated circuit including P-channel MOS transistors having different threshold voltages |
JP2758259B2 (ja) * | 1990-09-27 | 1998-05-28 | 株式会社東芝 | バッファ回路 |
JPH04281294A (ja) * | 1991-03-11 | 1992-10-06 | Matsushita Electric Ind Co Ltd | 駆動回路 |
US5602496A (en) * | 1992-06-17 | 1997-02-11 | Advanced Micro Devices, Inc. | Input buffer circuit including an input level translator with sleep function |
US5331228A (en) * | 1992-07-31 | 1994-07-19 | Sgs-Thomson Microelectronics, Inc. | Output driver circuit |
KR940010674B1 (ko) * | 1992-10-29 | 1994-10-24 | 삼성전자 주식회사 | 입력 버퍼 |
US5430393A (en) * | 1993-05-10 | 1995-07-04 | Motorola, Inc. | Integrated circuit with a low-power mode and clock amplifier circuit for same |
US5514979A (en) * | 1994-11-28 | 1996-05-07 | Unisys Corporation | Methods and apparatus for dynamically reducing ringing of driver output signal |
US5554942A (en) * | 1995-03-13 | 1996-09-10 | Motorola Inc. | Integrated circuit memory having a power supply independent input buffer |
GB2304244B (en) * | 1995-08-10 | 2000-01-26 | Advanced Risc Mach Ltd | Data processing system signal receiving buffers |
US5650733A (en) * | 1995-10-24 | 1997-07-22 | International Business Machines Corporation | Dynamic CMOS circuits with noise immunity |
JPH09321603A (ja) * | 1996-05-28 | 1997-12-12 | Oki Electric Ind Co Ltd | 多電源半導体集積回路 |
US5781034A (en) * | 1996-07-11 | 1998-07-14 | Cypress Semiconductor Corporation | Reduced output swing with p-channel pullup diode connected |
US6137313A (en) * | 1997-06-20 | 2000-10-24 | Altera Corporation | Resistive pull-up device for I/O pin |
JPH11145397A (ja) * | 1997-11-11 | 1999-05-28 | Mitsubishi Electric Corp | 半導体集積回路装置 |
US5942917A (en) * | 1997-12-29 | 1999-08-24 | Intel Corporation | High speed ratioed CMOS logic structures for a pulsed input environment |
US6225819B1 (en) | 1998-03-17 | 2001-05-01 | Cypress Semiconductor Corp. | Transmission line impedance matching output buffer |
US6163169A (en) * | 1998-08-13 | 2000-12-19 | International Business Machines Corporation | CMOS tri-state control circuit for a bidirectional I/O with slew rate control |
US6549038B1 (en) * | 2000-09-14 | 2003-04-15 | University Of Washington | Method of high-performance CMOS design |
US6384621B1 (en) | 2001-02-22 | 2002-05-07 | Cypress Semiconductor Corp. | Programmable transmission line impedance matching circuit |
DE10158112C1 (de) * | 2001-11-27 | 2003-06-26 | Texas Instruments Deutschland | Ausgangstreiberschaltung |
JP3902598B2 (ja) * | 2004-02-19 | 2007-04-11 | エルピーダメモリ株式会社 | 半導体回路装置 |
US7888962B1 (en) | 2004-07-07 | 2011-02-15 | Cypress Semiconductor Corporation | Impedance matching circuit |
JP2006303003A (ja) * | 2005-04-18 | 2006-11-02 | Toshiba Corp | プリント基板、および情報処理装置 |
US8036846B1 (en) | 2005-10-20 | 2011-10-11 | Cypress Semiconductor Corporation | Variable impedance sense architecture and method |
JP4690861B2 (ja) * | 2005-11-04 | 2011-06-01 | 新光電気工業株式会社 | 半導体モジュール及び半導体モジュール用放熱板 |
JP4680816B2 (ja) * | 2006-03-31 | 2011-05-11 | 三菱電機株式会社 | 半導体装置 |
JP4799296B2 (ja) * | 2006-06-30 | 2011-10-26 | 株式会社東芝 | 電子機器 |
US7724036B2 (en) * | 2007-09-06 | 2010-05-25 | Ashutosh Das | Clock guided logic with reduced switching |
US11539363B2 (en) * | 2020-06-10 | 2022-12-27 | Seiko Epson Corporation | Circuit device, oscillator, electronic apparatus, and vehicle |
IL311226A (en) * | 2021-09-13 | 2024-05-01 | Neologic Ltd | Implementation of logic gates with overflow tolerance |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4250406A (en) * | 1978-12-21 | 1981-02-10 | Motorola, Inc. | Single clock CMOS logic circuit with selected threshold voltages |
JPS5717223A (en) * | 1981-06-01 | 1982-01-28 | Toshiba Corp | Semiconductor integrated circuit |
JPS5949020A (ja) * | 1982-09-13 | 1984-03-21 | Toshiba Corp | 論理回路 |
US4525640A (en) * | 1983-03-31 | 1985-06-25 | Ibm Corporation | High performance and gate having an "natural" or zero threshold transistor for providing a faster rise time for the output |
US4584491A (en) * | 1984-01-12 | 1986-04-22 | Motorola, Inc. | TTL to CMOS input buffer circuit for minimizing power consumption |
US4682055A (en) * | 1986-03-17 | 1987-07-21 | Rca Corporation | CFET inverter having equal output signal rise and fall times by adjustment of the pull-up and pull-down transconductances |
JP2573320B2 (ja) * | 1988-07-11 | 1997-01-22 | 株式会社東芝 | 出力バッファ回路 |
-
1989
- 1989-07-28 JP JP1195951A patent/JPH07114359B2/ja not_active Expired - Lifetime
-
1990
- 1990-07-25 KR KR1019900011308A patent/KR930003926B1/ko not_active IP Right Cessation
- 1990-07-27 DE DE69023565T patent/DE69023565T2/de not_active Expired - Fee Related
- 1990-07-27 EP EP90114459A patent/EP0410473B1/en not_active Expired - Lifetime
- 1990-07-30 US US07/559,139 patent/US5073726A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5073726A (en) | 1991-12-17 |
EP0410473B1 (en) | 1995-11-15 |
KR930003926B1 (ko) | 1993-05-15 |
DE69023565D1 (de) | 1995-12-21 |
JPH07114359B2 (ja) | 1995-12-06 |
EP0410473A3 (en) | 1991-07-31 |
DE69023565T2 (de) | 1996-05-02 |
EP0410473A2 (en) | 1991-01-30 |
JPH0360218A (ja) | 1991-03-15 |
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Payment date: 20100428 Year of fee payment: 18 |
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