KR870007509A - 집적회로에서의 버퍼회로 - Google Patents

집적회로에서의 버퍼회로 Download PDF

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Publication number
KR870007509A
KR870007509A KR870000089A KR870000089A KR870007509A KR 870007509 A KR870007509 A KR 870007509A KR 870000089 A KR870000089 A KR 870000089A KR 870000089 A KR870000089 A KR 870000089A KR 870007509 A KR870007509 A KR 870007509A
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KR
South Korea
Prior art keywords
circuit
connection point
mos transistor
buffer circuit
buffer
Prior art date
Application number
KR870000089A
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English (en)
Other versions
KR900008439B1 (ko
Inventor
하루키 도다
나오카즈 미야와키
히로유키 고이누마
Original Assignee
와타리 스기이치로
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 와타리 스기이치로, 가부시키가이샤 도시바 filed Critical 와타리 스기이치로
Publication of KR870007509A publication Critical patent/KR870007509A/ko
Application granted granted Critical
Publication of KR900008439B1 publication Critical patent/KR900008439B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type
    • H03K19/09443—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type using a combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)

Abstract

내용 없음

Description

집적회로에서의 버퍼회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 관한 집적회로의 클록발생 회로를 나타낸 회로도.
제2도는 본 발명의 다른 실시예에 관한 클록 발생회로를 나타낸 회로도.
* 도면의 주요부분에 대한 부호의 설명
n-1…입력신호. p…프리챠지신호.
n…출력신호. Vcc,Vcc'…칩내부전원전위.
Vss,Vss'…칩내부 접지전위. BUF,BUF',…버퍼회로.
Q1,Q1'…부하용 트랜지스터. Q2,Q2'…구동용 트랜지스터.
Q3,Q3',Q4,Q4'…정전류용 트랜지스터. N1,N2,N1',N2'…입력접속점.
N3,N3'…출력접속점. C1,C2,C1',C2'…부하용량.
1,2…임피던스성분. R…저항성분.
L…인덕턱스성분. B,B'…버퍼회로.
i…출력전류.

Claims (3)

  1. 집적회로칩 내부의 전원전위 접속점과 접지전위 접속점 사이에 부하용 MOS트랜지스터및 구동용MOS트랜지스터가 직렬로 접속되어 있는 버퍼회로에 있어서.
    상기 양 트랜지스터 상호간의 출력접속 점과 상기 전원전위 접속점 사이및 상기 출력접속점과 상기 접지전위접속점 사이의 적어도 한쪽에 정전류회로가 부하용 MOS 트랜지스터 또는 구동용 MOS트랜지스터와 직렬로 접속되어진 것을 특징으로하는 집적회로에서의 버퍼회로.
  2. 제1항에 있어서, 상기 정전류회로는 게이트, 소오스가 상호 접속된 N챈널 공핍형 또는 P챈널 공핍형 MOS트랜지스터인 것을 특징으로 하는 집적 회로에서의 버퍼회로.
  3. 제1항에 있어서, 상기 버퍼회로가 다이나믹형 RAM에서의 프리챠지신호 발생회로의 최종출력단에 쓰여지도록 된 것을 특징으로 하는 집적회로에서의 버퍼회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019870000089A 1986-01-08 1987-01-08 집적회로에서의 버퍼회로 KR900008439B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1609 1986-01-08
JP61001609A JPS62159917A (ja) 1986-01-08 1986-01-08 集積回路におけるインバ−タ回路
JP61-1609 1986-01-08

Publications (2)

Publication Number Publication Date
KR870007509A true KR870007509A (ko) 1987-08-19
KR900008439B1 KR900008439B1 (ko) 1990-11-20

Family

ID=11506241

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870000089A KR900008439B1 (ko) 1986-01-08 1987-01-08 집적회로에서의 버퍼회로

Country Status (5)

Country Link
US (1) US4754170A (ko)
EP (1) EP0237139B1 (ko)
JP (1) JPS62159917A (ko)
KR (1) KR900008439B1 (ko)
DE (1) DE3770841D1 (ko)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234623A (ja) * 1987-03-23 1988-09-29 Toshiba Corp 半導体集積回路
US4791521A (en) * 1987-04-07 1988-12-13 Western Digital Corporation Method and apparatus for reducing transient noise by premagnetization of parasitic inductance
JPH01113993A (ja) * 1987-10-28 1989-05-02 Toshiba Corp 半導体集積回路
KR910004735B1 (ko) * 1988-07-18 1991-07-10 삼성전자 주식회사 데이타 출력용 버퍼회로
US4982108A (en) * 1988-08-02 1991-01-01 Motorola, Inc. Low current CMOS translator circuit
US5198699A (en) * 1988-09-09 1993-03-30 Texas Instruments Incorporated Capacitor-driven signal transmission circuit
US5023472A (en) * 1988-09-09 1991-06-11 Texas Instruments Incorporated Capacitor-driven signal transmission circuit
JPH0666674B2 (ja) * 1988-11-21 1994-08-24 株式会社東芝 半導体集積回路の出力回路
US4982120A (en) * 1989-07-03 1991-01-01 Dell Corporate Services Corporation Power supply decoupling mechanism for integrated circuits
US5041741A (en) * 1990-09-14 1991-08-20 Ncr Corporation Transient immune input buffer
JPH04146650A (ja) * 1990-10-08 1992-05-20 Mitsubishi Electric Corp 半導体集積回路装置
JP2617239B2 (ja) * 1990-11-07 1997-06-04 シャープ株式会社 ディジタル集積回路
JPH04317219A (ja) * 1991-04-17 1992-11-09 Mitsubishi Electric Corp 出力回路
EP0596637A1 (en) * 1992-11-02 1994-05-11 STMicroelectronics, Inc. Input buffer circuit
US5440258A (en) * 1994-02-08 1995-08-08 International Business Machines Corporation Off-chip driver with voltage regulated predrive
US6057702A (en) * 1995-08-24 2000-05-02 Nec Corporation Bus driver
US5703501A (en) * 1995-11-27 1997-12-30 Advanced Micro Devices, Inc. Apparatus and method for precharging a bus to an intermediate level
JPH10326131A (ja) * 1997-05-26 1998-12-08 Nec Corp バスドライバ
US6137316A (en) * 1998-06-09 2000-10-24 Siemens Aktiengesellschaft Integrated circuit with improved off chip drivers
JP2997241B1 (ja) * 1998-07-17 2000-01-11 株式会社半導体理工学研究センター 低スイッチング雑音論理回路
JP2010103837A (ja) * 2008-10-24 2010-05-06 Nec Electronics Corp 半導体装置
US10879899B2 (en) * 2017-08-15 2020-12-29 Realtek Semiconductor Corp. Clock buffer and method thereof

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3914702A (en) * 1973-06-01 1975-10-21 Rca Corp Complementary field-effect transistor amplifier
US4023122A (en) * 1975-01-28 1977-05-10 Nippon Electric Company, Ltd. Signal generating circuit
JPS5268304A (en) * 1975-12-05 1977-06-07 Fujitsu Ltd Transistor circuit
US4274014A (en) * 1978-12-01 1981-06-16 Rca Corporation Switched current source for current limiting complementary symmetry inverter
US4275313A (en) * 1979-04-09 1981-06-23 Bell Telephone Laboratories, Incorporated Current limiting output circuit with output feedback
US4398106A (en) * 1980-12-19 1983-08-09 International Business Machines Corporation On-chip Delta-I noise clamping circuit
JPS57106228A (en) * 1980-12-24 1982-07-02 Fujitsu Ltd Semiconductor circuit
US4394588A (en) * 1980-12-30 1983-07-19 International Business Machines Corporation Controllable di/dt push/pull driver
EP0057239B1 (de) * 1981-01-30 1985-02-13 Ibm Deutschland Gmbh Monolithisch integrierte Gegentakt-Treiberschaltung
JPS583328A (ja) * 1981-06-29 1983-01-10 Fujitsu Ltd 基板電圧発生回路
JPS583183A (ja) * 1981-06-30 1983-01-08 Fujitsu Ltd 半導体装置の出力回路
JPS58133038A (ja) * 1982-02-03 1983-08-08 Nec Corp インバ−タ回路
JPS595488A (ja) * 1982-07-01 1984-01-12 Fujitsu Ltd 半導体装置
US4516123A (en) * 1982-12-27 1985-05-07 At&T Bell Laboratories Integrated circuit including logic array with distributed ground connections
JPS59212027A (ja) * 1983-05-18 1984-11-30 Toshiba Corp 半導体集積回路の出力回路
JPS6030152A (ja) * 1983-07-28 1985-02-15 Toshiba Corp 集積回路
US4584491A (en) * 1984-01-12 1986-04-22 Motorola, Inc. TTL to CMOS input buffer circuit for minimizing power consumption
US4567378A (en) * 1984-06-13 1986-01-28 International Business Machines Corporation Driver circuit for controlling signal rise and fall in field effect transistor processors
US4609834A (en) * 1984-12-24 1986-09-02 Burroughs Corporation Integrated logic circuit incorporating a module which generates a control signal that cancels switching noise

Also Published As

Publication number Publication date
EP0237139A1 (en) 1987-09-16
US4754170A (en) 1988-06-28
JPS62159917A (ja) 1987-07-15
DE3770841D1 (de) 1991-07-25
KR900008439B1 (ko) 1990-11-20
EP0237139B1 (en) 1991-06-19

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