KR920006984A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

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Publication number
KR920006984A
KR920006984A KR1019910015412A KR910015412A KR920006984A KR 920006984 A KR920006984 A KR 920006984A KR 1019910015412 A KR1019910015412 A KR 1019910015412A KR 910015412 A KR910015412 A KR 910015412A KR 920006984 A KR920006984 A KR 920006984A
Authority
KR
South Korea
Prior art keywords
semiconductor memory
fet
memory device
channel mos
mos type
Prior art date
Application number
KR1019910015412A
Other languages
English (en)
Inventor
가즈타카 노가미
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR920006984A publication Critical patent/KR920006984A/ko

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음

Description

반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 내지 제3도는 본 발명의 1실시예에 따른 반도체기억장치의 회로구성을 나타낸 도면.

Claims (6)

  1. 크로스커플되어 워드선과 내부노드(ND1,ND2)사이에 접속된 한쌍의 FET(N1,N2;전계효과트랜지스터)와, 상기 내부노드(N1,N2)와 비트선사이에 접속된 한쌍의 다이오드(D1,D2)및 상기 내부노드(ND1,ND2)와 전압원(Vm)사이에 접속된 부하회로(L1,L2)를 갖춘 것을 특징으로 하는 반도체기억장치.
  2. 제1항에 있어서, 상기 FET는 N채널 MOS형 FET이며, 상기 다이오드는 애노드측이 상기 비트선에 접속되고 캐소드측이 상기 내부노드(ND1,ND2)에 접속되어 있는 것을 특징으로 하는 반도체기억장치.
  3. 제2항에 있어서, 상기 부하회로(L1,L2)는 저항소자(R1,R2)또는 크로스커플된 P채널 MOS형 FET로 이루어진 것을 특징으로 하는 반도체기억장치.
  4. 제1항에 있어서, 상기 FET는 P채널 MOS형 FET(P5, P6)이고, 상기 다이오드는 애노드측이 상기 내부노드(ND1,ND2)에 접속되는 캐소드측이 상기 비트선에 접속되어 있는 것을 특징으로 하는 반도체기억장치.
  5. 제4항에 있어서, 상기 부하회로(L3,L4)는 저항소자(R3,R4) 또는 크로스커플된 N채널 MOS형 FET(N5,N6)로 이루어진 것을 특징으로 하는 반도체 기억장치.
  6. 제1항 내지 제5항중 어느 한항에 있어서, 상기 전압원은 그 출력 전위가 상기 워드선에 인가되는 전위와 같은 위상으로 가변하는 것을 특징으로 하는 반도체기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910015412A 1990-09-04 1991-09-04 반도체 기억장치 KR920006984A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP02-232415 1990-09-04
JP2232415A JPH04113587A (ja) 1990-09-04 1990-09-04 半導体記憶装置

Publications (1)

Publication Number Publication Date
KR920006984A true KR920006984A (ko) 1992-04-28

Family

ID=16938897

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910015412A KR920006984A (ko) 1990-09-04 1991-09-04 반도체 기억장치

Country Status (3)

Country Link
US (1) US5267192A (ko)
JP (1) JPH04113587A (ko)
KR (1) KR920006984A (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5404326A (en) * 1992-06-30 1995-04-04 Sony Corporation Static random access memory cell structure having a thin film transistor load
US5457647A (en) * 1993-03-31 1995-10-10 Sgs-Thomson Microelectronics, Inc. Passive hierarchical bitline memory architecture which resides in metal layers of a SRAM array
US5363328A (en) * 1993-06-01 1994-11-08 Motorola Inc. Highly stable asymmetric SRAM cell
US5675533A (en) * 1994-09-26 1997-10-07 Texas Instruments Incorporated Semiconductor device
US5691934A (en) * 1995-07-13 1997-11-25 Douglass; Barry G. Memory cell and method of operation thereof
US5691935A (en) * 1995-07-13 1997-11-25 Douglass; Barry G. Memory element and method of operation thereof
US5804470A (en) * 1996-10-23 1998-09-08 Advanced Micro Devices, Inc. Method of making a selective epitaxial growth circuit load element
JP4805655B2 (ja) * 2005-10-28 2011-11-02 株式会社東芝 半導体記憶装置
JP5677394B2 (ja) 2012-09-28 2015-02-25 株式会社東芝 パスゲート及び半導体記憶装置
US10249361B2 (en) * 2014-01-14 2019-04-02 Nvidia Corporation SRAM write driver with improved drive strength

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2457921C2 (de) * 1974-12-07 1976-12-09 Ibm Deutschland Verfahren und schaltungsanordnung zur erhoehung der schreibgeschwindigkeit in integrierten datenspeichern
JPH02193395A (ja) * 1989-01-23 1990-07-31 Hitachi Ltd 半導体メモリおよびメモリセル

Also Published As

Publication number Publication date
JPH04113587A (ja) 1992-04-15
US5267192A (en) 1993-11-30

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