KR880010573A - 대규모 반도체 논리장치 - Google Patents

대규모 반도체 논리장치 Download PDF

Info

Publication number
KR880010573A
KR880010573A KR1019880000580A KR880000580A KR880010573A KR 880010573 A KR880010573 A KR 880010573A KR 1019880000580 A KR1019880000580 A KR 1019880000580A KR 880000580 A KR880000580 A KR 880000580A KR 880010573 A KR880010573 A KR 880010573A
Authority
KR
South Korea
Prior art keywords
stage
circuits
buffer circuits
buffer
scale semiconductor
Prior art date
Application number
KR1019880000580A
Other languages
English (en)
Other versions
KR900008023B1 (ko
Inventor
아키라 야마기와
도시히로 오카베
Original Assignee
미타 가츠시게
가부시키가이샤 히타치세이사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미타 가츠시게, 가부시키가이샤 히타치세이사쿠쇼 filed Critical 미타 가츠시게
Publication of KR880010573A publication Critical patent/KR880010573A/ko
Application granted granted Critical
Publication of KR900008023B1 publication Critical patent/KR900008023B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Microcomputers (AREA)

Abstract

내용 없음

Description

대규모 반도체 논리장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 논리장치의 일실시예를 나타내는 도면.
제2도는 버퍼회로의 일례를 나타내는 회로도.
제3A도, 제3B도는 버퍼회로의 접속변경을 설명하는 도면.

Claims (4)

  1. 다른 위상을 가진 복수의 클록신호에 의해서 동작하고, 하나의 칩 위에 배치되는 대규모 반도체 논리장치에 있어서, (A)상기 복수의 클록신호를 받는 복수의 입력단과, (B)상기 복수의 입력단의 각각 접속되어 적어도 3단의 직렬접속으로 이루어지는 복수의 버퍼회로와, 제1단 버퍼회로는 상기 입력단의 근방에 배치되어 상기 입력단과 접속하고, 제2단 버퍼회로는 상기 칩의 중앙부에 배치되는 상기 제1단 버퍼회로와 접속하고, 그리고 (C)상기 복수의 버퍼회로를 통해서 상기 복수의 클록신호를 받는 복수의 부하회로로 이루어지며, 상기 복수의 부하회로는 상기 복수의 버퍼회로의 최종단 버퍼회로와 접속하고, 상기 제2단 버퍼회로와 상기 최종단 버퍼회로와의 사이에 있어서 각 단의 버퍼회로 사이를 모두 실질적으로 같은 선로 길이가 되도록 배선하고, 각 단의 버퍼회로에 접속하는 다음 단의 버퍼회로의 수를 모두 같게 하고, 각 최종단 버퍼회로와 각 부하회로와의 사이의 선로길이를 모두 실질적으로 같게 배선하고, 각 최종단 버퍼회로에 접속하는 상기 부하회로의 수를 모두 같게 하여 이루어지는 대규모 반도체 논리장치.
  2. 제1항에 있어서, 상기 복수의 버퍼회로는 직렬접속한 4단의 버퍼회로로 이루어지며, 상기 최종단 버퍼회로는 제4단 버퍼회로이며, 제2단 버퍼회로는 중심으로 하여 상기 칩을 4개의 에리어로 구분했을 때에 제3단 버퍼회로를 상기 각 구분한 4개의 에리어의 각각의 중앙부에 배치한 대규모 반도체 논리장치.
  3. 제1항에 있어서, 상기 복수의 버퍼회로의 적어도 상기 복수의 최종단 버퍼회로의 각각은 CMOS논리소자이고, 이 CMOS논리소자는 N-MOS트랜지스터와, P-MOS트랜지스터부를 N-MOS트랜지스터부보다 그 치수를 크게 하고, 따라서 CMOS논리소자의 상승과 하강 레스폰스를 실질적으로 동일하게 한 대규모 반도체 논리장치.
  4. 제1항 내지 제3항중 어느 한항에 있어서, 다른 상의 클록신호를 받는 버퍼회로끼리를 각 그룹으로 해서 근접 배치하고, 이 그룹은 다른 전원라인을 통해서 각 그룹의 버퍼회로에 급전되는 대규모 반도체 논리장치.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880000580A 1987-02-23 1988-01-26 대규모 반도체 논리장치 KR900008023B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP62037951A JPH083773B2 (ja) 1987-02-23 1987-02-23 大規模半導体論理回路
JP87-37951 1987-02-23
JP62-37951 1987-02-23

Publications (2)

Publication Number Publication Date
KR880010573A true KR880010573A (ko) 1988-10-10
KR900008023B1 KR900008023B1 (ko) 1990-10-29

Family

ID=12511856

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880000580A KR900008023B1 (ko) 1987-02-23 1988-01-26 대규모 반도체 논리장치

Country Status (4)

Country Link
US (1) US4812684A (ko)
JP (1) JPH083773B2 (ko)
KR (1) KR900008023B1 (ko)
CN (1) CN1009520B (ko)

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03505031A (ja) * 1988-05-06 1991-10-31 マジエラン・コーポレーシヨン・（オーストラリア）・プロプライエタリイ・リミテツド 低電力クロツク回路
US5239215A (en) * 1988-05-16 1993-08-24 Matsushita Electric Industrial Co., Ltd. Large scale integrated circuit configured to eliminate clock signal skew effects
JPH0736422B2 (ja) * 1988-08-19 1995-04-19 株式会社東芝 クロック供給回路
JP2685546B2 (ja) * 1988-11-16 1997-12-03 株式会社日立製作所 クロック分配回路の製造方法
JPH02205908A (ja) * 1989-02-03 1990-08-15 Nec Corp データ処理装置
JPH0824143B2 (ja) * 1989-02-08 1996-03-06 株式会社東芝 集積回路の配置配線方式
JP2622612B2 (ja) * 1989-11-14 1997-06-18 三菱電機株式会社 集積回路
US5077676A (en) * 1990-03-30 1991-12-31 International Business Machines Corporation Reducing clock skew in large-scale integrated circuits
US5218240A (en) * 1990-11-02 1993-06-08 Concurrent Logic, Inc. Programmable logic cell and array with bus repeaters
JPH04253211A (ja) * 1991-01-29 1992-09-09 Fujitsu Ltd クロックデューティ補正回路
US5109168A (en) * 1991-02-27 1992-04-28 Sun Microsystems, Inc. Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits
US5264746A (en) * 1991-05-16 1993-11-23 Nec Corporation Logic circuit board with a clock observation circuit
JP3026387B2 (ja) * 1991-08-23 2000-03-27 沖電気工業株式会社 半導体集積回路
JPH05233092A (ja) * 1992-02-18 1993-09-10 Nec Ic Microcomput Syst Ltd クロック信号分配方法および分配回路
US5428764A (en) * 1992-04-24 1995-06-27 Digital Equipment Corporation System for radial clock distribution and skew regulation for synchronous clocking of components of a computing system
US5296748A (en) * 1992-06-24 1994-03-22 Network Systems Corporation Clock distribution system
JP3048471B2 (ja) * 1992-09-08 2000-06-05 沖電気工業株式会社 クロック供給回路及びクロックスキュー調整方法
US5355035A (en) * 1993-01-08 1994-10-11 Vora Madhukar B High speed BICMOS switches and multiplexers
US6002268A (en) * 1993-01-08 1999-12-14 Dynachip Corporation FPGA with conductors segmented by active repeaters
JPH06244282A (ja) * 1993-02-15 1994-09-02 Nec Corp 半導体集積回路装置
JP3318084B2 (ja) * 1993-05-07 2002-08-26 三菱電機株式会社 信号供給回路
US5467033A (en) * 1993-07-02 1995-11-14 Tandem Computers Incorporated Chip clock skew control method and apparatus
US5448208A (en) * 1993-07-15 1995-09-05 Nec Corporation Semiconductor integrated circuit having an equal propagation delay
JP3112784B2 (ja) * 1993-09-24 2000-11-27 日本電気株式会社 クロック信号分配回路
JP2699831B2 (ja) * 1993-10-21 1998-01-19 日本電気株式会社 クロック分配回路
JP2540762B2 (ja) * 1993-11-10 1996-10-09 日本電気株式会社 クロック信号供給方法
US5691662A (en) * 1994-04-07 1997-11-25 Hitachi Microsystems, Inc. Method for minimizing clock skew in integrated circuits and printed circuits
US5570045A (en) * 1995-06-07 1996-10-29 Lsi Logic Corporation Hierarchical clock distribution system and method
US5831459A (en) * 1995-11-13 1998-11-03 International Business Machines Corporation Method and system for adjusting a clock signal within electronic circuitry
US6157237A (en) * 1996-05-01 2000-12-05 Sun Microsystems, Inc. Reduced skew control block clock distribution network
US6137316A (en) * 1998-06-09 2000-10-24 Siemens Aktiengesellschaft Integrated circuit with improved off chip drivers
US6573757B1 (en) 2000-09-11 2003-06-03 Cypress Semiconductor Corp. Signal line matching technique for ICS/PCBS
US8103496B1 (en) 2000-10-26 2012-01-24 Cypress Semicondutor Corporation Breakpoint control in an in-circuit emulation system
US6724220B1 (en) 2000-10-26 2004-04-20 Cyress Semiconductor Corporation Programmable microcontroller architecture (mixed analog/digital)
US8176296B2 (en) 2000-10-26 2012-05-08 Cypress Semiconductor Corporation Programmable microcontroller architecture
US7765095B1 (en) 2000-10-26 2010-07-27 Cypress Semiconductor Corporation Conditional branching in an in-circuit emulation system
US7023257B1 (en) * 2000-10-26 2006-04-04 Cypress Semiconductor Corp. Architecture for synchronizing and resetting clock signals supplied to multiple programmable analog blocks
US8160864B1 (en) 2000-10-26 2012-04-17 Cypress Semiconductor Corporation In-circuit emulator and pod synchronized boot
US8149048B1 (en) 2000-10-26 2012-04-03 Cypress Semiconductor Corporation Apparatus and method for programmable power management in a programmable analog circuit block
US7406674B1 (en) 2001-10-24 2008-07-29 Cypress Semiconductor Corporation Method and apparatus for generating microcontroller configuration information
US8078970B1 (en) 2001-11-09 2011-12-13 Cypress Semiconductor Corporation Graphical user interface with user-selectable list-box
US8042093B1 (en) 2001-11-15 2011-10-18 Cypress Semiconductor Corporation System providing automatic source code generation for personalization and parameterization of user modules
US6971004B1 (en) 2001-11-19 2005-11-29 Cypress Semiconductor Corp. System and method of dynamically reconfiguring a programmable integrated circuit
US8069405B1 (en) 2001-11-19 2011-11-29 Cypress Semiconductor Corporation User interface for efficiently browsing an electronic document using data-driven tabs
US7770113B1 (en) 2001-11-19 2010-08-03 Cypress Semiconductor Corporation System and method for dynamically generating a configuration datasheet
US7844437B1 (en) * 2001-11-19 2010-11-30 Cypress Semiconductor Corporation System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit
US7774190B1 (en) 2001-11-19 2010-08-10 Cypress Semiconductor Corporation Sleep and stall in an in-circuit emulation system
US8103497B1 (en) 2002-03-28 2012-01-24 Cypress Semiconductor Corporation External interface for event architecture
US7308608B1 (en) 2002-05-01 2007-12-11 Cypress Semiconductor Corporation Reconfigurable testing system and method
US7761845B1 (en) 2002-09-09 2010-07-20 Cypress Semiconductor Corporation Method for parameterizing a user module
US7295049B1 (en) 2004-03-25 2007-11-13 Cypress Semiconductor Corporation Method and circuit for rapid alignment of signals
US8069436B2 (en) 2004-08-13 2011-11-29 Cypress Semiconductor Corporation Providing hardware independence to automate code generation of processing device firmware
US8286125B2 (en) 2004-08-13 2012-10-09 Cypress Semiconductor Corporation Model for a hardware device-independent method of defining embedded firmware for programmable systems
US7332976B1 (en) 2005-02-04 2008-02-19 Cypress Semiconductor Corporation Poly-phase frequency synthesis oscillator
US7336115B2 (en) * 2005-02-09 2008-02-26 International Business Machines Corporation Redundancy in signal distribution trees
US7400183B1 (en) 2005-05-05 2008-07-15 Cypress Semiconductor Corporation Voltage controlled oscillator delay cell and method
US8089461B2 (en) 2005-06-23 2012-01-03 Cypress Semiconductor Corporation Touch wake for electronic devices
US20070074412A1 (en) * 2005-09-30 2007-04-05 Roert Kahute Adjustable, Mobile, Vertical Practice Target Support Platform
US8085067B1 (en) 2005-12-21 2011-12-27 Cypress Semiconductor Corporation Differential-to-single ended signal converter circuit and method
US8067948B2 (en) 2006-03-27 2011-11-29 Cypress Semiconductor Corporation Input/output multiplexer bus
US7479819B2 (en) * 2006-12-14 2009-01-20 International Business Machines Corporation Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees
US20080229265A1 (en) * 2006-12-14 2008-09-18 International Business Machines Corporation Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
US20080229266A1 (en) * 2006-12-14 2008-09-18 International Business Machines Corporation Design Structure for a Clock Distribution Network, Structure, and Method for Providing Balanced Loading in Integrated Circuit Clock Trees
US7511548B2 (en) * 2006-12-14 2009-03-31 International Business Machines Corporation Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees
US8040266B2 (en) 2007-04-17 2011-10-18 Cypress Semiconductor Corporation Programmable sigma-delta analog-to-digital converter
US8092083B2 (en) 2007-04-17 2012-01-10 Cypress Semiconductor Corporation Temperature sensor with digital bandgap
US8026739B2 (en) 2007-04-17 2011-09-27 Cypress Semiconductor Corporation System level interconnect with programmable switching
US8130025B2 (en) 2007-04-17 2012-03-06 Cypress Semiconductor Corporation Numerical band gap
US7737724B2 (en) 2007-04-17 2010-06-15 Cypress Semiconductor Corporation Universal digital block interconnection and channel routing
US9564902B2 (en) 2007-04-17 2017-02-07 Cypress Semiconductor Corporation Dynamically configurable and re-configurable data path
US8516025B2 (en) * 2007-04-17 2013-08-20 Cypress Semiconductor Corporation Clock driven dynamic datapath chaining
US8065653B1 (en) 2007-04-25 2011-11-22 Cypress Semiconductor Corporation Configuration of programmable IC design elements
US8266575B1 (en) 2007-04-25 2012-09-11 Cypress Semiconductor Corporation Systems and methods for dynamically reconfiguring a programmable system on a chip
US9720805B1 (en) 2007-04-25 2017-08-01 Cypress Semiconductor Corporation System and method for controlling a target device
US8049569B1 (en) 2007-09-05 2011-11-01 Cypress Semiconductor Corporation Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes
US9448964B2 (en) 2009-05-04 2016-09-20 Cypress Semiconductor Corporation Autonomous control in a programmable system
EP2849022B1 (en) * 2013-09-12 2016-05-25 Socionext Inc. Circuitry useful for clock generation and distribution
US10234891B2 (en) * 2016-03-16 2019-03-19 Ricoh Company, Ltd. Semiconductor integrated circuit, and method for supplying clock signals in semiconductor integrated circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5580136A (en) * 1978-12-14 1980-06-17 Fujitsu Ltd Clock signal distribution system
JPS59212027A (ja) * 1983-05-18 1984-11-30 Toshiba Corp 半導体集積回路の出力回路
JPS6030152A (ja) * 1983-07-28 1985-02-15 Toshiba Corp 集積回路
US4700088A (en) * 1983-08-05 1987-10-13 Texas Instruments Incorporated Dummy load controlled multilevel logic single clock logic circuit
JP2564787B2 (ja) * 1983-12-23 1996-12-18 富士通株式会社 ゲートアレー大規模集積回路装置及びその製造方法
JPH0656876B2 (ja) * 1984-12-28 1994-07-27 富士通株式会社 半導体装置
US4742254A (en) * 1985-10-07 1988-05-03 Nippon Gakki Seizo Kabushiki Kaisha CMOS integrated circuit for signal delay
US4682055A (en) * 1986-03-17 1987-07-21 Rca Corporation CFET inverter having equal output signal rise and fall times by adjustment of the pull-up and pull-down transconductances
US4761567A (en) * 1987-05-20 1988-08-02 Advanced Micro Devices, Inc. Clock scheme for VLSI systems

Also Published As

Publication number Publication date
KR900008023B1 (ko) 1990-10-29
JPS63205720A (ja) 1988-08-25
US4812684A (en) 1989-03-14
JPH083773B2 (ja) 1996-01-17
CN88100886A (zh) 1988-09-07
CN1009520B (zh) 1990-09-05

Similar Documents

Publication Publication Date Title
KR880010573A (ko) 대규모 반도체 논리장치
KR900013616A (ko) 집적회로의 배치배선방식
KR850005059A (ko) 스위칭 잡음을 감소시킨 lsi 게이트 어레이
KR870009400A (ko) 검사하기에 용이한 반도체 lsi장치
KR910006844A (ko) 다중 i/o 선택 메모리 모듈
KR950012663A (ko) 경계주사 테스트 회로를 가진 반도체 장치
KR890004321A (ko) 로직마크로 및 랜덤억세스메모리 마크로를 구비한 반도체 집적회로장치
KR880011797A (ko) 반도체 기억장치
KR860002866A (ko) 반도체 집적회로장치
KR880010422A (ko) 반도체 기억장치
KR960006977B1 (ko) 마스터-슬라이스형 반도체집적회로
KR890016630A (ko) 전력용 반도체장치
US4093993A (en) Bit-slice type large scale integrated circuit with multiple functions on a one-chip semiconductor device
KR970071255A (ko) 인터록 선입선출 제어 회로
KR970051297A (ko) 메모리 회로의 평행 출력 버퍼
KR880010497A (ko) 마스터 슬라이스형 집적회로
KR880004483A (ko) 데이타 버스 리세트 회로를 구비한 반도체 기억장치
KR900019036A (ko) 반도체기억장치
US4757218A (en) Semiconductor IC device with word lines shielded from voltage changes in adjacent lines
KR900008190B1 (ko) 반도체집적회로장치
US6097043A (en) Semiconductor integrated circuit and supply method for supplying multiple supply voltages in a semiconductor integrated circuit
KR860007666A (ko) 복수 메모리셀 어레이용 공통 구동회로를 갖는 반도체 메모리 장치
JPH05300007A (ja) ２入力ｏｒ回路
KR0157340B1 (ko) 반도체 메모리 소자의 셀 어레이의 배열방법
KR910007134A (ko) 페일-세이프(fail-safe) 회로를 갖는 웨이퍼 스캐일 반도체 장치

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20031006

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee