JPS5580136A - Clock signal distribution system - Google Patents

Clock signal distribution system

Info

Publication number
JPS5580136A
JPS5580136A JP15514478A JP15514478A JPS5580136A JP S5580136 A JPS5580136 A JP S5580136A JP 15514478 A JP15514478 A JP 15514478A JP 15514478 A JP15514478 A JP 15514478A JP S5580136 A JPS5580136 A JP S5580136A
Authority
JP
Japan
Prior art keywords
circuit
pulse width
clock signal
fixed
rounding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15514478A
Other languages
Japanese (ja)
Inventor
Tatsuro Yoshimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15514478A priority Critical patent/JPS5580136A/en
Publication of JPS5580136A publication Critical patent/JPS5580136A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To eliminate undesired variation in pulse width by shortening a period while avoiding an influence of the rounding of a waveform, etc., in transmission, by providing a frequency multiplier circuit and chopper circuit which shorten pulse width to fixed width near a load circuit.
CONSTITUTION: On printed substrate 1, several integrated-circuit elements LSI4 are packaged and in the center, clock signal distributor 5 is provided which distributes clocks from clock generator 7 to respective circuit elements 4. Near latch circuit 11 which forms a load on circuit elements 4 receiving clock signals from distributor 5, chopper circuit 10 is provided which compresses pulse width to fixed width, and this circuit 10 is composed of a circuit of NOR gate circuits 12W14 or inverters combined and two-input NOR circuit 15 serving as a frequency multiplier circuit; and the duty ratio of a clock signal generated by generator 7 is fixed to approximate 50%, and consequently the rounding of a waveform and variation in pulse width caused by components in substrate 1 and wiring are prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP15514478A 1978-12-14 1978-12-14 Clock signal distribution system Pending JPS5580136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15514478A JPS5580136A (en) 1978-12-14 1978-12-14 Clock signal distribution system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15514478A JPS5580136A (en) 1978-12-14 1978-12-14 Clock signal distribution system

Publications (1)

Publication Number Publication Date
JPS5580136A true JPS5580136A (en) 1980-06-17

Family

ID=15599494

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15514478A Pending JPS5580136A (en) 1978-12-14 1978-12-14 Clock signal distribution system

Country Status (1)

Country Link
JP (1) JPS5580136A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151622A (en) * 1982-03-05 1983-09-08 Fujitsu Ltd Microprocessor
JPS5988738U (en) * 1982-11-30 1984-06-15 ソニー株式会社 Microcomputer clock signal generation circuit
JPS63205720A (en) * 1987-02-23 1988-08-25 Hitachi Ltd Large scale semiconductor logic circuit
JPH01157115A (en) * 1987-12-14 1989-06-20 Hitachi Ltd Semiconductor integrated circuit device
JPH01502222A (en) * 1987-06-30 1989-08-03 ユニシス・コーポレーション Automatic clock deskew on circuit board
FR2773020A1 (en) * 1997-12-24 1999-06-25 Sgs Thomson Microelectronics Clock distribution circuit for integrated circuits
US7471124B2 (en) 2006-03-28 2008-12-30 Fujitsu Limited Chopper circuit that chops edge of control signal

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58151622A (en) * 1982-03-05 1983-09-08 Fujitsu Ltd Microprocessor
JPH0522249B2 (en) * 1982-03-05 1993-03-29 Fujitsu Ltd
JPS5988738U (en) * 1982-11-30 1984-06-15 ソニー株式会社 Microcomputer clock signal generation circuit
JPS63205720A (en) * 1987-02-23 1988-08-25 Hitachi Ltd Large scale semiconductor logic circuit
US4812684A (en) * 1987-02-23 1989-03-14 Hitachi, Ltd. Multiphase clock distribution for VLSI chip
JPH01502222A (en) * 1987-06-30 1989-08-03 ユニシス・コーポレーション Automatic clock deskew on circuit board
JPH0577087B2 (en) * 1987-06-30 1993-10-26 Unisys Corp
JPH01157115A (en) * 1987-12-14 1989-06-20 Hitachi Ltd Semiconductor integrated circuit device
FR2773020A1 (en) * 1997-12-24 1999-06-25 Sgs Thomson Microelectronics Clock distribution circuit for integrated circuits
US6252449B1 (en) 1997-12-24 2001-06-26 Stmicroelectronics S.A. Clock distribution circuit in an integrated circuit
US7471124B2 (en) 2006-03-28 2008-12-30 Fujitsu Limited Chopper circuit that chops edge of control signal

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