KR910006844A - 다중 i/o 선택 메모리 모듈 - Google Patents

다중 i/o 선택 메모리 모듈 Download PDF

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KR910006844A
KR910006844A KR1019900015512A KR900015512A KR910006844A KR 910006844 A KR910006844 A KR 910006844A KR 1019900015512 A KR1019900015512 A KR 1019900015512A KR 900015512 A KR900015512 A KR 900015512A KR 910006844 A KR910006844 A KR 910006844A
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data
additional
memory
module
circuit
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KR1019900015512A
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KR100220000B1 (ko
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에이치. 닐 요셉
에이. 포티트 케네스
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엔. 라이스 미레트
텍사스 인스트루먼츠 인코포레이티드
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

내용 없음

Description

다중 I/O 선택 메모리 모듈
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 다중 CAS입력을 포함하는 반도체 메모리 디바이스를 도시한 도면.
제3도는 제2도의 디바이스를 상세하게 도시한 도면.
제4도는 제2도의 디바이스를 더욱 상세하게 도시한 도면.

Claims (9)

  1. 다수의 이산 메모리 회로로 형성되고 상기 회로상에 장착된 개별회로에 의해 제공된 것보다 높은 메모리 밀도 요구량을 만족시키는데 사용된 메모리 모듈에 있어서, 4비트의 정수배와 같은 전장을 갖는 개별 스트링을 제공하도록 각각 구성되고, 개별 스트링 전장을 합과 같은 전장을 갖는 조합 데이타 스트링을 제공하도록 정렬되며, 개별 데이타 스트링의 전송을 제어하도록 접속된 신호 라인을 포함하는 다수의 이산 데이타 메모리 회로 조합 데이타 스트링의 상이한 비트에 각각 관련되고, 상기 모듈로부터 출력시키기 위해 메모리 회로들중 한 회로로부터 개별 스트링들중 한 스트링에 관련된 자료를 전송하도록 접속되는 다수의 데이타 핀, 메모리 회로들중 한 회로로부터 개별 데이타 스트링들중 한 스트링의 전송을 개시하기 위해 외부 신호를 수신하도록 제어핀에 접속된 각각의 신호 라인을 갖는 다수의 제어핀, 및 다수의 추가 신호 라인 및 다수의 추가 데이타 라인을 갖는 추가 메모리 회로를 포함하고, 제1의 추가 라인의 개별 데이타 스트링이 제1메모리 회로로부터 전송될때 추가 데이타 라인들중 한 라인을 따라 데이타 비트를 전송하는데 응답하여 상기 추가 회로를 제공하기 위해 제1의 데이타 메모리 회로의 신호 라인에 공통으로 배선 접속되며, 제2의 추가 신호 라인의 개별 데이타 스트링이 제2메모리 회로로부터 전송될때 추가 데이타 라인들중 한 라인을 따라 데이타의 비트를 전송하는 데 응답하여 상기 추가 회로를 제공하기 위해 제2의 데이타 메모리 회로의 신호 라인에 공통으로 재선 접속되는 것을 특징으로 하는 모듈.
  2. 제1항에 있어서, 모든 메모리 회로가 동적 등속 호출 메모리 회로이고 상기 추가 회로가 패리티 데이타의 전송을 제어하는 4개의 신호 라인을 포함하는 것을 특징으로 하는 모듈.
  3. 제1항에 있어서, 이산 데이타 메모리 회로가 8비트의 정수배인 데이타 스트링 전장을 제공하기 위한 쌍으로 정렬되고, 상기 다수의 데이타 메모리 회로가 개별 데이타 스트링 전장의 합과 같은 전장을 갖는 조합 데이타 스트링을 제공하도록 정렬되는 것을 특징으로 하는 모듈.
  4. 제1항에 있어서, 제1의 추가 신호 라인이 9비트의 배수인 데이타 스트링 전장을 제공하기 위해 제3데이타 메모리 회로들중 제3의 회로의 신호라인에 공통으로 배선 접속되며, 제2의 개별 데이타 라인이 9비트의 배수인 데이타 스트링 전장을 제공하기 위해 제4데이타 메모리 회로들중 제4의 회로의 신호 라인에 공통으로 배선 접속되는 것을 특징으로 하는 모듈.
  5. 제1항에 있어서, 추가 메모리 회로내의 추가 신호 라인과 추가 데이타 라인의 수가 동일한 것을 특징으로 하는 모듈.
  6. 제1항에 있어서, 추가 메모리 회로내의 데이타 라인의 수가 4개인 것을 특징으로 하는 모듈.
  7. 제1항에 있어서, 추가 메모리 회로내의 신호 라인의 수가 4개인 것을 특징으로 하는 모듈.
  8. 제1항에 있어서, 각각의 추가 데이타 라인이 제9데이타 비트를 조합 데이타 스트링내의 각각의 8개의 비트를 결합시키도록 배선 접속되는 것을 특징으로 하는 모듈.
  9. 제1항에 있어서, 추가 데이타 라인이 조합 데이타 워드의 8비트마다 패리티 데이타의 1비트를 결합시키도록 배선 접속되는 것을 특징으로 하는 모듈.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900015512A 1989-09-29 1990-09-28 데이타와 패리티 비트용으로 정렬된 메모리 모듈 KR100220000B1 (ko)

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Application Number Priority Date Filing Date Title
US415,074 1989-09-29
US07415074 US5089993B1 (en) 1989-09-29 1989-09-29 Memory module arranged for data and parity bits

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KR910006844A true KR910006844A (ko) 1991-04-30
KR100220000B1 KR100220000B1 (ko) 1999-09-01

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US (2) US5089993B1 (ko)
EP (2) EP0419863B1 (ko)
JP (1) JP2942610B2 (ko)
KR (1) KR100220000B1 (ko)
CN (1) CN1024858C (ko)
DE (2) DE69033061T2 (ko)

Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6028795A (en) * 1985-09-24 2000-02-22 Hitachi, Ltd. One chip semiconductor integrated circuit device having two modes of data write operation and bits setting operation
US5923591A (en) * 1985-09-24 1999-07-13 Hitachi, Ltd. Memory circuit
US5450342A (en) * 1984-10-05 1995-09-12 Hitachi, Ltd. Memory device
US5448519A (en) * 1984-10-05 1995-09-05 Hitachi, Ltd. Memory device
JPH03248243A (ja) * 1990-02-26 1991-11-06 Nec Corp 情報処理装置
US5257233A (en) * 1990-10-31 1993-10-26 Micron Technology, Inc. Low power memory module using restricted RAM activation
JPH05182454A (ja) * 1991-06-25 1993-07-23 Mitsubishi Electric Corp デュアルポートメモリ装置
US5550782A (en) * 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
US20020130681A1 (en) * 1991-09-03 2002-09-19 Cliff Richard G. Programmable logic array integrated circuits
US5883850A (en) * 1991-09-03 1999-03-16 Altera Corporation Programmable logic array integrated circuits
US5633830A (en) * 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
JP3241110B2 (ja) * 1991-12-26 2001-12-25 株式会社東芝 半導体記憶装置
US5164916A (en) * 1992-03-31 1992-11-17 Digital Equipment Corporation High-density double-sided multi-string memory module with resistor for insertion detection
US5270964A (en) * 1992-05-19 1993-12-14 Sun Microsystems, Inc. Single in-line memory module
US5371866A (en) * 1992-06-01 1994-12-06 Staktek Corporation Simulcast standard multichip memory addressing system
JP3073610B2 (ja) * 1992-09-22 2000-08-07 株式会社東芝 半導体記憶装置
US5272664A (en) * 1993-04-21 1993-12-21 Silicon Graphics, Inc. High memory capacity DRAM SIMM
US5377144A (en) * 1993-07-27 1994-12-27 Texas Instruments Inc. Memory array reconfiguration for testing
US5355377A (en) * 1993-11-23 1994-10-11 Tetra Assoc. Inc. Auto-selectable self-parity generator
US5412613A (en) * 1993-12-06 1995-05-02 International Business Machines Corporation Memory device having asymmetrical CAS to data input/output mapping and applications thereof
US5504700A (en) * 1994-02-22 1996-04-02 Sun Microsystems, Inc. Method and apparatus for high density sixteen and thirty-two megabyte single in-line memory module
US5612965A (en) * 1994-04-26 1997-03-18 Unisys Corporation Multiple memory bit/chip failure detection
US5432678A (en) * 1994-05-12 1995-07-11 Texas Instruments Incorporated High power dissipation vertical mounted package for surface mount application
US5802540A (en) * 1995-11-08 1998-09-01 Altera Corporation Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices
US5798961A (en) * 1994-08-23 1998-08-25 Emc Corporation Non-volatile memory module
US5465237A (en) * 1994-12-01 1995-11-07 Advanced Peripherals Labs, Inc. RAS encoded generator for a memory bank
US5513135A (en) * 1994-12-02 1996-04-30 International Business Machines Corporation Synchronous memory packaged in single/dual in-line memory module and method of fabrication
US5701313A (en) * 1995-02-24 1997-12-23 Unisys Corporation Method and apparatus for removing soft errors from a memory
US5666371A (en) * 1995-02-24 1997-09-09 Unisys Corporation Method and apparatus for detecting errors in a system that employs multi-bit wide memory elements
US5511164A (en) 1995-03-01 1996-04-23 Unisys Corporation Method and apparatus for determining the source and nature of an error within a computer system
KR0144901B1 (ko) * 1995-04-24 1998-08-17 김광호 트리플 포트 반도체 메모리장치
KR960039006A (ko) * 1995-04-26 1996-11-21 김광호 디램버스에 접속가능한 불휘발성 반도체 메모리장치
IN188196B (ko) * 1995-05-15 2002-08-31 Silicon Graphics Inc
US5686730A (en) * 1995-05-15 1997-11-11 Silicon Graphics, Inc. Dimm pair with data memory and state memory
JP3386924B2 (ja) * 1995-05-22 2003-03-17 株式会社日立製作所 半導体装置
US5590071A (en) * 1995-11-16 1996-12-31 International Business Machines Corporation Method and apparatus for emulating a high capacity DRAM
US6240535B1 (en) 1995-12-22 2001-05-29 Micron Technology, Inc. Device and method for testing integrated circuit dice in an integrated circuit module
US5796746A (en) * 1995-12-22 1998-08-18 Micron Technology, Inc. Device and method for testing integrated circuit dice in an integrated circuit module
US5819304A (en) * 1996-01-29 1998-10-06 Iowa State University Research Foundation, Inc. Random access memory assembly
US5729497A (en) * 1996-02-27 1998-03-17 Micron Technology Inc. Method of using parity and ECC bits to increase the yield of non-parity ECC devices
US5991850A (en) 1996-08-15 1999-11-23 Micron Technology, Inc. Synchronous DRAM modules including multiple clock out signals for increasing processing speed
US6128215A (en) * 1997-08-19 2000-10-03 Altera Corporation Static random access memory circuits
US6072332A (en) * 1997-10-14 2000-06-06 Altera Corporation Variable depth memories for programmable logic devices
FR2771526B1 (fr) * 1997-11-27 2004-07-23 Bull Sa Architecture pour la gestion de donnees vitales dans une machine multi-modulaire et procede pour la mise en oeuvre d'une telle architecture
US7007130B1 (en) * 1998-02-13 2006-02-28 Intel Corporation Memory system including a memory module having a memory module controller interfacing between a system memory controller and memory devices of the memory module
WO1999030240A1 (en) 1997-12-05 1999-06-17 Intel Corporation Memory system including a memory module having a memory module controller
US6970968B1 (en) * 1998-02-13 2005-11-29 Intel Corporation Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module
US7024518B2 (en) * 1998-02-13 2006-04-04 Intel Corporation Dual-port buffer-to-memory interface
US6968419B1 (en) * 1998-02-13 2005-11-22 Intel Corporation Memory module having a memory module controller controlling memory transactions for a plurality of memory devices
US5870325A (en) * 1998-04-14 1999-02-09 Silicon Graphics, Inc. Memory system with multiple addressing and control busses
US6467017B1 (en) 1998-06-23 2002-10-15 Altera Corporation Programmable logic device having embedded dual-port random access memory configurable as single-port memory
US6061263A (en) * 1998-12-29 2000-05-09 Intel Corporation Small outline rambus in-line memory module
US6414868B1 (en) 1999-06-07 2002-07-02 Sun Microsystems, Inc. Memory expansion module including multiple memory banks and a bank control circuit
US6643752B1 (en) * 1999-12-09 2003-11-04 Rambus Inc. Transceiver with latency alignment circuitry
US6243315B1 (en) 1999-12-31 2001-06-05 James B. Goodman Computer memory system with a low power down mode
US7363422B2 (en) 2000-01-05 2008-04-22 Rambus Inc. Configurable width buffered module
US7266634B2 (en) * 2000-01-05 2007-09-04 Rambus Inc. Configurable width buffered module having flyby elements
US7356639B2 (en) * 2000-01-05 2008-04-08 Rambus Inc. Configurable width buffered module having a bypass circuit
US6502161B1 (en) 2000-01-05 2002-12-31 Rambus Inc. Memory system including a point-to-point linked memory subsystem
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US7017002B2 (en) * 2000-01-05 2006-03-21 Rambus, Inc. System featuring a master device, a buffer device and a plurality of integrated circuit memory devices
US6725314B1 (en) 2001-03-30 2004-04-20 Sun Microsystems, Inc. Multi-bank memory subsystem employing an arrangement of multiple memory modules
US6720796B1 (en) 2001-05-06 2004-04-13 Altera Corporation Multiple size memories in a programmable logic device
US7111110B1 (en) 2002-12-10 2006-09-19 Altera Corporation Versatile RAM for programmable logic device
US6996686B2 (en) * 2002-12-23 2006-02-07 Sun Microsystems, Inc. Memory subsystem including memory modules having multiple banks
JP4478922B2 (ja) * 2003-08-29 2010-06-09 旭有機材工業株式会社 作動流体用継手の受口およびその受口を有する弁
JP2007529821A (ja) * 2004-03-15 2007-10-25 トムソン ライセンシング 効率的なビデオのリサンプリング方法
US7464225B2 (en) * 2005-09-26 2008-12-09 Rambus Inc. Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology
US11328764B2 (en) 2005-09-26 2022-05-10 Rambus Inc. Memory system topologies including a memory die stack
US7562271B2 (en) 2005-09-26 2009-07-14 Rambus Inc. Memory system topologies including a buffer device and an integrated circuit memory device
US7349233B2 (en) * 2006-03-24 2008-03-25 Intel Corporation Memory device with read data from different banks
KR100684740B1 (ko) * 2006-10-30 2007-02-22 삼성에스디아이 주식회사 이차 전지
JP2010218641A (ja) * 2009-03-18 2010-09-30 Elpida Memory Inc メモリモジュール
CN103502913B (zh) 2011-01-05 2015-08-26 雷蛇(亚太)私人有限公司 用于能显示的键盘、键区或其它用户输入设备的透光键组件
US20150019802A1 (en) * 2013-07-11 2015-01-15 Qualcomm Incorporated Monolithic three dimensional (3d) random access memory (ram) array architecture with bitcell and logic partitioning

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4081701A (en) * 1976-06-01 1978-03-28 Texas Instruments Incorporated High speed sense amplifier for MOS random access memory
US4375665A (en) * 1978-04-24 1983-03-01 Texas Instruments Incorporated Eight bit standard connector bus for sixteen bit microcomputer using mirrored memory boards
JPS5588154A (en) * 1978-12-27 1980-07-03 Fujitsu Ltd Data storage method
US4371963A (en) * 1980-12-24 1983-02-01 Ncr Corporation Method and apparatus for detecting and correcting errors in a memory
US4453251A (en) * 1981-10-13 1984-06-05 Burroughs Corporation Error-correcting memory with low storage overhead and fast correction mechanism
JPS58128089A (ja) * 1981-12-26 1983-07-30 Fujitsu Ltd 半導体記憶装置
US4656605A (en) * 1983-09-02 1987-04-07 Wang Laboratories, Inc. Single in-line memory module
JPS60179984A (ja) * 1984-02-27 1985-09-13 Nec Corp メモリ回路方式
JPS60183653A (ja) * 1984-03-01 1985-09-19 Toshiba Corp ビツト・エラ−検出機能を備えたメモリ
US4658377A (en) * 1984-07-26 1987-04-14 Texas Instruments Incorporated Dynamic memory array with segmented bit lines
EP0523760B1 (en) * 1985-01-22 1997-06-04 Texas Instruments Incorporated Serial accessed semiconductor memory
US4636986B1 (en) * 1985-01-22 1999-12-07 Texas Instruments Inc Separately addressable memory arrays in a multiple array semiconductor chip
US4797850A (en) * 1986-05-12 1989-01-10 Advanced Micro Devices, Inc. Dynamic random access memory controller with multiple independent control channels
JPS63163645A (ja) * 1986-12-26 1988-07-07 Ricoh Co Ltd 二次元配列メモリ装置
JP2763772B2 (ja) * 1987-07-15 1998-06-11 オリンパス光学工業株式会社 コネクタ装置

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EP0419863A3 (en) 1992-07-15
EP0677849B1 (en) 1999-04-14
KR100220000B1 (ko) 1999-09-01
EP0419863B1 (en) 1996-01-10
JPH03205682A (ja) 1991-09-09
JP2942610B2 (ja) 1999-08-30
US5228132B1 (en) 1998-12-01
US5089993A (en) 1992-02-18
DE69033061T2 (de) 1999-10-21
CN1051634A (zh) 1991-05-22
DE69024730T2 (de) 1996-08-14
US5228132A (en) 1993-07-13
US5089993B1 (en) 1998-12-01
EP0677849A3 (en) 1996-02-28
DE69033061D1 (de) 1999-05-20
CN1024858C (zh) 1994-06-01
EP0419863A2 (en) 1991-04-03
DE69024730D1 (de) 1996-02-22
EP0677849A2 (en) 1995-10-18

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