JP7426702B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP7426702B2 JP7426702B2 JP2020022429A JP2020022429A JP7426702B2 JP 7426702 B2 JP7426702 B2 JP 7426702B2 JP 2020022429 A JP2020022429 A JP 2020022429A JP 2020022429 A JP2020022429 A JP 2020022429A JP 7426702 B2 JP7426702 B2 JP 7426702B2
- Authority
- JP
- Japan
- Prior art keywords
- pad
- semiconductor chip
- resistor
- signal processing
- processing circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims description 142
- 230000008054 signal transmission Effects 0.000 description 35
- 238000010586 diagram Methods 0.000 description 29
- 230000000052 comparative effect Effects 0.000 description 19
- 230000003071 parasitic effect Effects 0.000 description 15
- 239000002131 composite material Substances 0.000 description 7
- 230000005611 electricity Effects 0.000 description 6
- 230000003068 static effect Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000002542 deteriorative effect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/4917—Crossed wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
図1は、第1比較例の半導体装置211の構成を示す図である。この半導体装置211は、半導体チップ10Xおよびパッケージ20を備え、信号伝送路3を伝送されて来た信号を受信するものである。
図3は、第2比較例の半導体装置221の構成を示す図である。この半導体装置221は、半導体チップ10Yおよびパッケージ20を備え、信号伝送路3を伝送されて来た信号を受信するものである。第1比較例の半導体装置211の構成(図1)と比べると、第2比較例の半導体装置221の構成(図3)は、信号処理回路11の信号入力端が2つのパッド14,15に接続されている点で相違する。半導体チップ10Y上においてパッド14とパッド15とは互いに短絡している。パッケージ20の端子21は、ボンディングワイヤ31によりパッド14と接続され、ボンディングワイヤ32によりパッド15と接続されている。
図5は、第1実施形態の半導体装置111の構成を示す図である。この半導体装置111は、半導体チップ10Aおよびパッケージ20を備え、信号伝送路3を伝送されて来た信号を受信するものである。
この(2)式においてsをjωに置き換えて角周波数ωで表現すると、合成インピーダンスZは下記(2)式で表される。jは虚数単位である。合成インピーダンスZの絶対値は下記(3)式で表される。ωRCの値は1と比べて十分に小さいとしてよいから、(3)式は下記(4)式で近似することができる。
この(4)式から分かるように、L=R2Cとすれば、合成インピーダンスZはRと等しくなる。或いは、LをR2Cに近い値にすれば、合成インピーダンスZはRに近い値になる。L、RおよびCの各値を適切に設定すればよい。例えば、L=1nH、R=50Ωとすると、C=400fFとすればよく、或いは、Cを400fFに近い値にすればよい。このようにすることにより、ボンディングワイヤの寄生インダクタンスの影響を低減することができる。
図8は、第2実施形態の半導体装置121の構成を示す図である。この半導体装置121は、半導体チップ10Bおよびパッケージ20を備え、信号伝送路3を伝送されて来た信号を受信するものである。第1実施形態における半導体チップ10Aと比較すると、第2実施形態における半導体チップ10Bは、第2抵抗器17を更に有する点で相違する。第2抵抗器17は、電源電位を供給する基準電位供給端と第2パッド15との間に設けられている。
図10は、第3実施形態の半導体装置131の構成を示す図である。この半導体装置131は、半導体チップ10Cおよびパッケージ20を備え、信号伝送路3を伝送されて来た信号を受信するものである。第1実施形態における半導体チップ10Aと比較すると、第3実施形態における半導体チップ10Cは、第3抵抗器18を更に有する点で相違する。第3抵抗器18は、第1パッド14と第2パッド15との間に設けられている。
一方、第1実施形態における前述の(4)式を変形すると下記(9)式のようになる。(8)式と(9)式とを比較すると、下記(10)式で表される因子の有無の点で相違している。この(10)式の値は1より小さいので、第1実施形態と比べて第3実施形態では、ボンディングワイヤの寄生インピーダンスの影響を容易に低減することができる。
図12は、第4実施形態の半導体装置141の構成を示す図である。この半導体装置141は、半導体チップ10Dおよびパッケージ20を備え、信号伝送路3を伝送されて来た信号を受信するものである。第2実施形態における半導体チップ10Bと比較すると、第4実施形態における半導体チップ10Dは、第3抵抗器18を更に有する点で相違する。第3抵抗器18は、第1パッド14と第2パッド15との間に設けられている。
図14は、第5実施形態の半導体装置151および第4抵抗器40を備える受信装置1の構成を示す図である。半導体装置151は、半導体チップ10Eおよびパッケージ20を備え、信号伝送路3を伝送されて来た信号を受信するものである。第1実施形態における半導体チップ10Aと比較すると、第5実施形態における半導体チップ10Eは、第1抵抗器16を有していない点で相違する。受信装置1は、半導体チップ内の第1抵抗器16に替えて、電源電位を供給する基準電位供給欄と端子21との間に設けられた第4抵抗器40を備えている。
Claims (8)
- 信号処理回路、複数のパッドおよび第1抵抗器を有し、前記複数のパッドのうちの第1パッドと第2パッドとが互いに短絡しておらず、前記第1パッドと基準電位供給端との間に前記第1抵抗器が設けられ、前記第2パッドが前記信号処理回路の信号入力端または信号出力端と接続されている半導体チップと、
前記半導体チップを搭載し、外部との間で信号を入力または出力する複数の端子を有するパッケージと、
を備え、
前記パッケージの前記複数の端子のうちの何れかの特定端子が、第1ボンディングワイヤにより前記第1パッドと接続され、第2ボンディングワイヤにより前記第2パッドと接続されている、
半導体装置。 - 前記半導体チップは、前記第2パッドと基準電位供給端との間に設けられた第2抵抗器を有する、
請求項1に記載の半導体装置。 - 前記半導体チップは、前記第1パッドと前記第2パッドとの間に設けられた第3抵抗器を有する、
請求項1または2項に記載の半導体装置。 - 信号処理回路および複数のパッドを有し、前記複数のパッドのうちの第1パッドと第2パッドとが互いに短絡しておらず、前記第2パッドが前記信号処理回路の信号入力端と接続されている半導体チップと、
前記半導体チップを搭載し、外部との間で信号を入力または出力する複数の端子を有するパッケージと、
前記パッケージの前記複数の端子のうちの何れかの特定端子と基準電位供給端との間に設けられた第4抵抗器と、
を備え、
前記パッケージの前記特定端子が、第1ボンディングワイヤにより前記第1パッドと接続され、第2ボンディングワイヤにより前記第2パッドと接続されている、
受信装置。 - 信号処理回路および複数のパッドを有し、前記複数のパッドのうちの第1パッドと第2パッドとが互いに短絡しておらず、前記第2パッドが前記信号処理回路の信号出力端と接続されている半導体チップと、
前記半導体チップを搭載し、外部との間で信号を入力または出力する複数の端子を有するパッケージと、
前記パッケージの前記複数の端子のうちの何れかの特定端子と基準電位供給端との間に設けられた第5抵抗器と、
を備え、
前記パッケージの前記特定端子が、第1ボンディングワイヤにより前記第1パッドと接続され、第2ボンディングワイヤにより前記第2パッドと接続されている、
送信装置。 - 前記半導体チップは、前記第1パッドと接続されたESD保護素子を有する、
請求項1~3の何れか1項に記載の半導体装置。 - 前記半導体チップは、前記第1パッドと接続されたESD保護素子を有する、
請求項4に記載の受信装置。 - 前記半導体チップは、前記第1パッドと接続されたESD保護素子を有する、
請求項5に記載の送信装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020022429A JP7426702B2 (ja) | 2020-02-13 | 2020-02-13 | 半導体装置 |
CN202110147832.6A CN113258549A (zh) | 2020-02-13 | 2021-02-03 | 半导体装置、接收装置以及发送装置 |
KR1020210017022A KR20210103416A (ko) | 2020-02-13 | 2021-02-05 | 반도체 장치, 수신 장치, 및, 송신 장치 |
US17/171,331 US11508686B2 (en) | 2020-02-13 | 2021-02-09 | Semiconductor device, receiver and transmitter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020022429A JP7426702B2 (ja) | 2020-02-13 | 2020-02-13 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2021129009A JP2021129009A (ja) | 2021-09-02 |
JP7426702B2 true JP7426702B2 (ja) | 2024-02-02 |
Family
ID=77180841
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2020022429A Active JP7426702B2 (ja) | 2020-02-13 | 2020-02-13 | 半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US11508686B2 (ja) |
JP (1) | JP7426702B2 (ja) |
KR (1) | KR20210103416A (ja) |
CN (1) | CN113258549A (ja) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010000427A1 (en) | 1999-02-25 | 2001-04-26 | Miller Charles A. | Method of incorporating interconnect systems into an integrated circuit process flow |
JP2003526901A (ja) | 1999-02-25 | 2003-09-09 | フォームファクター,インコーポレイテッド | 集積回路の相互接続システム |
JP2014045004A (ja) | 2012-08-24 | 2014-03-13 | Samsung Electro-Mechanics Co Ltd | Esd保護回路及び電子機器 |
US20170033574A1 (en) | 2015-07-30 | 2017-02-02 | Mitsumi Electric Co., Ltd. | Multichip, battery protection apparatus, and battery pack |
JP2017034065A (ja) | 2015-07-31 | 2017-02-09 | 富士通株式会社 | 半導体装置 |
JP2018017605A (ja) | 2016-07-28 | 2018-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置及びそれを備えた半導体システム |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2531827B2 (ja) * | 1990-04-25 | 1996-09-04 | 株式会社東芝 | 半導体装置及びその製造方法 |
KR100270817B1 (ko) | 1997-05-22 | 2000-11-01 | 이해영 | 초고주파소자 실장 패키지 및 그 패키지에 사용되는 본딩와이어의 기생효과 감소방법 |
US20100253435A1 (en) | 2004-03-18 | 2010-10-07 | Ikuroh Ichitsubo | Rf power amplifier circuit utilizing bondwires in impedance matching |
JP5138338B2 (ja) * | 2007-11-02 | 2013-02-06 | ルネサスエレクトロニクス株式会社 | 半導体パッケージ |
US20100109053A1 (en) * | 2008-11-04 | 2010-05-06 | Ching-Han Jan | Semiconductor device having integrated circuit with pads coupled by external connecting component and method for modifying integrated circuit |
JP5591594B2 (ja) * | 2009-07-13 | 2014-09-17 | ローム株式会社 | 半導体デバイス |
US8427799B2 (en) | 2011-02-04 | 2013-04-23 | Intersil Americas Inc. | ESD clamp for multi-bonded pins |
US10163767B2 (en) * | 2013-10-11 | 2018-12-25 | Mediatek Inc. | Semiconductor package |
JP2015100034A (ja) * | 2013-11-19 | 2015-05-28 | ヤマハ株式会社 | Icチップ |
JP6145038B2 (ja) * | 2013-12-26 | 2017-06-07 | 株式会社東芝 | Dc−dcコンバータ、および、半導体集積回路 |
TWI566347B (zh) * | 2014-03-24 | 2017-01-11 | 智原科技股份有限公司 | 積體電路 |
JP2017045915A (ja) * | 2015-08-28 | 2017-03-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9570446B1 (en) * | 2015-10-08 | 2017-02-14 | Samsung Electronics Co., Ltd. | Semiconductor device |
JP7219563B2 (ja) * | 2018-07-20 | 2023-02-08 | ローム株式会社 | 半導体装置 |
JP2020035804A (ja) * | 2018-08-28 | 2020-03-05 | ルネサスエレクトロニクス株式会社 | 半導体装置、電子回路および半導体装置の検査方法 |
-
2020
- 2020-02-13 JP JP2020022429A patent/JP7426702B2/ja active Active
-
2021
- 2021-02-03 CN CN202110147832.6A patent/CN113258549A/zh active Pending
- 2021-02-05 KR KR1020210017022A patent/KR20210103416A/ko active Search and Examination
- 2021-02-09 US US17/171,331 patent/US11508686B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010000427A1 (en) | 1999-02-25 | 2001-04-26 | Miller Charles A. | Method of incorporating interconnect systems into an integrated circuit process flow |
JP2003526901A (ja) | 1999-02-25 | 2003-09-09 | フォームファクター,インコーポレイテッド | 集積回路の相互接続システム |
JP2014045004A (ja) | 2012-08-24 | 2014-03-13 | Samsung Electro-Mechanics Co Ltd | Esd保護回路及び電子機器 |
US20170033574A1 (en) | 2015-07-30 | 2017-02-02 | Mitsumi Electric Co., Ltd. | Multichip, battery protection apparatus, and battery pack |
JP2017034792A (ja) | 2015-07-30 | 2017-02-09 | ミツミ電機株式会社 | マルチチップ、電池保護装置及び電池パック |
JP2017034065A (ja) | 2015-07-31 | 2017-02-09 | 富士通株式会社 | 半導体装置 |
JP2018017605A (ja) | 2016-07-28 | 2018-02-01 | ルネサスエレクトロニクス株式会社 | 半導体装置及びそれを備えた半導体システム |
US20180034404A1 (en) | 2016-07-28 | 2018-02-01 | Renesas Electronics Corporation | Semiconductor device and semiconductor system equipped with the same |
Also Published As
Publication number | Publication date |
---|---|
US11508686B2 (en) | 2022-11-22 |
CN113258549A (zh) | 2021-08-13 |
KR20210103416A (ko) | 2021-08-23 |
JP2021129009A (ja) | 2021-09-02 |
US20210257328A1 (en) | 2021-08-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI414053B (zh) | 前端整合之被動式等化器及其方法 | |
JP2991636B2 (ja) | 半導体パッケージの基板への実装構造 | |
US8351170B2 (en) | Impedance compensated electrostatic discharge circuit for protection of high-speed interfaces and method of using the same | |
US8254071B2 (en) | Method and apparatus of providing 2-stage ESD protection for high-speed interfaces | |
JP7426702B2 (ja) | 半導体装置 | |
US7224180B2 (en) | Methods and systems for rise-time improvements in differential signal outputs | |
JPH07321828A (ja) | 電子装置 | |
CN109391257A (zh) | 接口电路 | |
US20100103573A1 (en) | Semiconductor package having electrostatic protection circuit for semiconductor package including multiple semiconductor chips | |
JP5026993B2 (ja) | 半導体装置及びその装置の信号終端方法 | |
US20150271914A1 (en) | Integrated circuit | |
JP2005086662A (ja) | 半導体装置 | |
US6300677B1 (en) | Electronic assembly having improved power supply bus voltage integrity | |
US7495975B2 (en) | Memory system including on-die termination unit having inductor | |
JP7046981B2 (ja) | Icチップ | |
US7763966B2 (en) | Resin molded semiconductor device and differential amplifier circuit | |
US6686762B2 (en) | Memory module using DRAM package to match channel impedance | |
US8907528B2 (en) | Semiconductor device | |
JP2003289149A (ja) | 受光モジュール | |
US10396719B2 (en) | Integrated circuit device | |
WO2016092833A1 (ja) | 電子回路、及び、電子回路の実装方法 | |
JPH0613421A (ja) | 集積回路装置 | |
TW503519B (en) | Integrated circuit interconnect system | |
US20070215988A1 (en) | Semiconductor Device Including a Plurality of Semiconductor Chips Packaged in a Common Housing | |
US6366131B1 (en) | System and method for increasing a drive signal and decreasing a pin count |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20221129 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20230921 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20230926 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20231006 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20240109 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20240116 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 7426702 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |