JP2005086662A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2005086662A JP2005086662A JP2003318434A JP2003318434A JP2005086662A JP 2005086662 A JP2005086662 A JP 2005086662A JP 2003318434 A JP2003318434 A JP 2003318434A JP 2003318434 A JP2003318434 A JP 2003318434A JP 2005086662 A JP2005086662 A JP 2005086662A
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- Prior art keywords
- pair
- circuit
- output
- signal
- semiconductor chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0278—Arrangements for impedance matching
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/028—Arrangements specific to the transmitter end
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】半導体チップ50又は50A内に構成される差動信号出力回路であって、差動信号が出力する一対の信号線30,40のそれぞれの信号線の出力端子12,13と該出力端子がそれぞれ接続するパッド31,41との間に抵抗R,Rを挿入する。抵抗R,Rは半導体チップ50又は50Aの内部に設けるものであって、特に、ボンディングワイヤやリードフレーム等のインダクタンス成分Lと配線容量等の容量成分Cの間に抵抗成分R,Rを入れると、非常に効果がある。
【選択図】 図1
Description
Claims (4)
- 半導体チップ内に配設され、一対の出力端子から差動信号を送出する出力回路と、前記半導体チップにおいて、前記一対の出力端子と半導体チップの外部回路に接続される一対のパッドとの間に配設され、配線に基づくインダクタンス成分及び容量成分を有し、前記差動信号を前記一対のパッドに導く一対の信号線と、を具備した半導体装置であって、
前記一対の信号線上にそれぞれ直列に抵抗を設けたことを特徴とする半導体装置。 - 半導体チップ内に配設され、一対の出力端子から差動信号を送出する出力回路と、前記半導体チップにおいて、前記一対の出力端子と半導体チップの外部回路に接続される一対のパッドとの間に配設され、配線に基づくインダクタンス成分及び容量成分を有し、前記差動信号を前記一対のパッドに導く一対の信号線と、を具備した半導体装置であって、
前記出力回路の内部にあって、前記一対の出力端子までの一対の出力信号線上にそれぞれ直列に抵抗を設けたことを特徴とする半導体装置。 - 半導体チップ内に配設され、一対の出力端子から差動信号を送出する出力回路と、前記半導体チップにおいて、前記一対の出力端子と半導体チップの外部回路に接続される一対のパッドとの間に配設され、配線に基づくインダクタンス成分及び容量成分を有し、前記差動信号を前記一対のパッドに導く一対の信号線と、前記一対の信号線上に設けられて、前記一対のパッドに接続する前記外部回路とのインタフェース機能を備えたI/Oセルと、を具備した半導体装置であって、
前記I/Oセルと前記一対のパッドとの間の信号線上に直列に抵抗を設けたことを特徴とする半導体装置。 - 前記抵抗は、半導体プロセスで作成されるポリシリコン抵抗又は拡散抵抗であることを特徴とする請求項1〜3のいずれか1つに記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003318434A JP2005086662A (ja) | 2003-09-10 | 2003-09-10 | 半導体装置 |
US10/937,896 US20050104649A1 (en) | 2003-09-10 | 2004-09-09 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003318434A JP2005086662A (ja) | 2003-09-10 | 2003-09-10 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005086662A true JP2005086662A (ja) | 2005-03-31 |
Family
ID=34417723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003318434A Withdrawn JP2005086662A (ja) | 2003-09-10 | 2003-09-10 | 半導体装置 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20050104649A1 (ja) |
JP (1) | JP2005086662A (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009252844A (ja) * | 2008-04-02 | 2009-10-29 | Denso Corp | 半導体装置 |
KR101396295B1 (ko) | 2006-12-20 | 2014-05-19 | 소니 주식회사 | 클록 공급장치 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9071220B2 (en) * | 2013-03-07 | 2015-06-30 | Qualcomm Incorporated | Efficient N-factorial differential signaling termination network |
US9313058B2 (en) | 2013-03-07 | 2016-04-12 | Qualcomm Incorporated | Compact and fast N-factorial single data rate clock and data recovery circuits |
US9337997B2 (en) | 2013-03-07 | 2016-05-10 | Qualcomm Incorporated | Transcoding method for multi-wire signaling that embeds clock information in transition of signal state |
US9374216B2 (en) | 2013-03-20 | 2016-06-21 | Qualcomm Incorporated | Multi-wire open-drain link with data symbol transition based clocking |
US9203599B2 (en) | 2014-04-10 | 2015-12-01 | Qualcomm Incorporated | Multi-lane N-factorial (N!) and other multi-wire communication systems |
US9755818B2 (en) | 2013-10-03 | 2017-09-05 | Qualcomm Incorporated | Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes |
US9735948B2 (en) | 2013-10-03 | 2017-08-15 | Qualcomm Incorporated | Multi-lane N-factorial (N!) and other multi-wire communication systems |
US9710412B2 (en) * | 2014-05-15 | 2017-07-18 | Qualcomm Incorporated | N-factorial voltage mode driver |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3872437A (en) * | 1972-12-12 | 1975-03-18 | Robertshaw Controls Co | Supervisory control system |
JPH01113993A (ja) * | 1987-10-28 | 1989-05-02 | Toshiba Corp | 半導体集積回路 |
JP2902016B2 (ja) * | 1989-11-21 | 1999-06-07 | 株式会社日立製作所 | 信号伝送方法および回路 |
US5264744A (en) * | 1989-11-21 | 1993-11-23 | Hitachi, Ltd. | Complementary signal transmission circuit with impedance matching circuitry |
JPH07235952A (ja) * | 1993-12-28 | 1995-09-05 | Oki Electric Ind Co Ltd | 信号伝送回路およびその回路を用いた信号伝送装置 |
JP2748865B2 (ja) * | 1994-09-27 | 1998-05-13 | 日本電気株式会社 | 出力回路 |
US5715287A (en) * | 1995-10-18 | 1998-02-03 | 3Com Corporation | Method and apparatus for dual purpose twisted pair interface circuit for multiple speed media in a network |
JP3719618B2 (ja) * | 1996-06-17 | 2005-11-24 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
US5781028A (en) * | 1996-06-21 | 1998-07-14 | Microsoft Corporation | System and method for a switched data bus termination |
US6072340A (en) * | 1997-03-24 | 2000-06-06 | Tellabs Operations, Inc. | Pulse shaping and filtering circuit for digital pulse data transmissions |
AU2439999A (en) * | 1998-04-23 | 1999-11-08 | Matsushita Electric Industrial Co., Ltd. | Method of designing power supply circuit and semiconductor chip |
US6552564B1 (en) * | 1999-08-30 | 2003-04-22 | Micron Technology, Inc. | Technique to reduce reflections and ringing on CMOS interconnections |
JP2002314397A (ja) * | 2001-04-17 | 2002-10-25 | Seiko Epson Corp | 差動信号出力回路 |
JP3808335B2 (ja) * | 2001-07-26 | 2006-08-09 | エルピーダメモリ株式会社 | メモリモジュール |
US7145413B2 (en) * | 2003-06-10 | 2006-12-05 | International Business Machines Corporation | Programmable impedance matching circuit and method |
US6949810B2 (en) * | 2003-10-14 | 2005-09-27 | Intel Corporation | Active phase cancellation for power delivery |
-
2003
- 2003-09-10 JP JP2003318434A patent/JP2005086662A/ja not_active Withdrawn
-
2004
- 2004-09-09 US US10/937,896 patent/US20050104649A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101396295B1 (ko) | 2006-12-20 | 2014-05-19 | 소니 주식회사 | 클록 공급장치 |
JP2009252844A (ja) * | 2008-04-02 | 2009-10-29 | Denso Corp | 半導体装置 |
JP4536788B2 (ja) * | 2008-04-02 | 2010-09-01 | 株式会社デンソー | 半導体装置 |
Also Published As
Publication number | Publication date |
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US20050104649A1 (en) | 2005-05-19 |
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