DE3477312D1 - Masterslice semiconductor device - Google Patents

Masterslice semiconductor device

Info

Publication number
DE3477312D1
DE3477312D1 DE8484304668T DE3477312T DE3477312D1 DE 3477312 D1 DE3477312 D1 DE 3477312D1 DE 8484304668 T DE8484304668 T DE 8484304668T DE 3477312 T DE3477312 T DE 3477312T DE 3477312 D1 DE3477312 D1 DE 3477312D1
Authority
DE
Germany
Prior art keywords
semiconductor device
masterslice semiconductor
masterslice
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484304668T
Other languages
English (en)
Inventor
Shinji C O Fujitsu Limite Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP58125289A external-priority patent/JPS6017931A/ja
Priority claimed from JP58125288A external-priority patent/JPS6017930A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3477312D1 publication Critical patent/DE3477312D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE8484304668T 1983-07-09 1984-07-09 Masterslice semiconductor device Expired DE3477312D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58125289A JPS6017931A (ja) 1983-07-09 1983-07-09 マスタ・スライス方式に於ける基本セル
JP58125288A JPS6017930A (ja) 1983-07-09 1983-07-09 マスタ・スライス方式に於ける基本セル

Publications (1)

Publication Number Publication Date
DE3477312D1 true DE3477312D1 (de) 1989-04-20

Family

ID=26461759

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484304668T Expired DE3477312D1 (de) 1983-07-09 1984-07-09 Masterslice semiconductor device

Country Status (4)

Country Link
US (1) US4816887A (de)
EP (1) EP0131463B1 (de)
KR (1) KR890004568B1 (de)
DE (1) DE3477312D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0695570B2 (ja) * 1985-02-07 1994-11-24 三菱電機株式会社 半導体集積回路装置
EP0224887B1 (de) * 1985-12-06 1992-03-11 Siemens Aktiengesellschaft Gate Array Anordnung in CMOS-Technik
EP0278463B1 (de) * 1987-02-09 1994-07-27 Fujitsu Limited Gatematrix mit in Verbindungsgebiet begrabenem Transistor
JPS6412577A (en) * 1987-07-06 1989-01-17 Canon Kk Thin film transistor
JPH0194636A (ja) * 1987-10-06 1989-04-13 Hitachi Ltd 半導体装置
EP0394598B1 (de) * 1989-04-28 1996-03-06 International Business Machines Corporation Gate-Array-Zelle, bestehend aus FET's von verschiedener und optimierter Grösse
JPH0383375A (ja) * 1989-08-25 1991-04-09 Sony Corp 半導体装置
JPH03234059A (ja) * 1990-02-09 1991-10-18 Sony Corp 半導体メモリ
US5289021A (en) * 1990-05-15 1994-02-22 Siarc Basic cell architecture for mask programmable gate array with 3 or more size transistors
US5055716A (en) * 1990-05-15 1991-10-08 Siarc Basic cell for bicmos gate array
WO1992002957A1 (en) * 1990-08-10 1992-02-20 Seiko Epson Corporation Semiconductor device
JP3038939B2 (ja) * 1991-02-08 2000-05-08 日産自動車株式会社 半導体装置
US5440153A (en) * 1994-04-01 1995-08-08 United Technologies Corporation Array architecture with enhanced routing for linear asics
US5552333A (en) * 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
US5723883A (en) * 1995-11-14 1998-03-03 In-Chip Gate array cell architecture and routing scheme
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
JP3152635B2 (ja) * 1996-09-09 2001-04-03 三洋電機株式会社 マスタスライス方式の基本セル、半導体集積回路装置、フリップフロップ回路、排他的論理和回路、マルチプレクサ及び加算器
US6445049B1 (en) * 1997-06-30 2002-09-03 Artisan Components, Inc. Cell based array comprising logic, transfer and drive cells
US6974978B1 (en) * 1999-03-04 2005-12-13 Intel Corporation Gate array architecture
JP3647323B2 (ja) * 1999-07-30 2005-05-11 富士通株式会社 半導体集積回路
US6617621B1 (en) 2000-06-06 2003-09-09 Virage Logic Corporation Gate array architecture using elevated metal levels for customization
JP2006156929A (ja) * 2004-04-19 2006-06-15 Fujitsu Ltd 半導体集積回路及びその設計方法
US8533641B2 (en) 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
JPS5864047A (ja) * 1981-10-13 1983-04-16 Nec Corp マスタ−スライス半導体集積回路装置
JPS5897847A (ja) * 1981-12-08 1983-06-10 Nec Corp 集積回路装置
JPS58139446A (ja) * 1982-02-15 1983-08-18 Nec Corp 半導体集積回路装置
US4513307A (en) * 1982-05-05 1985-04-23 Rockwell International Corporation CMOS/SOS transistor gate array apparatus

Also Published As

Publication number Publication date
EP0131463A3 (en) 1986-04-09
KR890004568B1 (ko) 1989-11-15
EP0131463A2 (de) 1985-01-16
EP0131463B1 (de) 1989-03-15
KR850000796A (ko) 1985-03-09
US4816887A (en) 1989-03-28

Similar Documents

Publication Publication Date Title
DE3473973D1 (de) Masterslice semiconductor device
DE3479943D1 (de) A masterslice semiconductor device
DE3485409D1 (de) Halbleiterschaltvorrichtung.
BR8401736A (pt) Dispositivo fotovoltaico
DE3477312D1 (de) Masterslice semiconductor device
SE8105257L (sv) Halvledaranordning
DE3482935D1 (de) Halbleiterlaservorrichtung.
KR850004169A (ko) Soi형 반도체장치 제조방법
KR900008927A (ko) 반도체 집적회로
DE3484514D1 (de) Halbleiterspeichergeraet.
KR850006779A (ko) 반도체 장치
KR850001613A (ko) 반도체 메모리
DE3484232D1 (de) Halbleiterspeichervorrichtung.
DE3584799D1 (de) Halbleitervorrichtung.
DE3581370D1 (de) Halbleitervorrichtung.
IT1176163B (it) Dispositivo assortitore
IT8322373A0 (it) Dispositivo semiconduttore.
DE3486418D1 (de) Halbleiterspeicheranordnung
DE3586568D1 (de) Halbleitereinrichtung.
DE3484817D1 (de) Halbleiteranordnung.
KR860004470A (ko) 반도체 장치
IT8124803A0 (it) Dispositivo semiconduttore
DE3485537D1 (de) Halbleiter-laservorrichtung.
KR840005919A (ko) 반도체 장치
ATA225484A (de) Strahlungsempfindliche halbleiteranordnung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition