KR850000796A - 마스터슬라이스형 반도체장치 - Google Patents

마스터슬라이스형 반도체장치

Info

Publication number
KR850000796A
KR850000796A KR1019840003972A KR840003972A KR850000796A KR 850000796 A KR850000796 A KR 850000796A KR 1019840003972 A KR1019840003972 A KR 1019840003972A KR 840003972 A KR840003972 A KR 840003972A KR 850000796 A KR850000796 A KR 850000796A
Authority
KR
South Korea
Prior art keywords
semiconductor device
type semiconductor
slice type
master slice
master
Prior art date
Application number
KR1019840003972A
Other languages
English (en)
Other versions
KR890004568B1 (ko
Inventor
신지 사또
Original Assignee
후지쑤가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP58125288A external-priority patent/JPS6017930A/ja
Priority claimed from JP58125289A external-priority patent/JPS6017931A/ja
Application filed by 후지쑤가부시끼가이샤 filed Critical 후지쑤가부시끼가이샤
Publication of KR850000796A publication Critical patent/KR850000796A/ko
Application granted granted Critical
Publication of KR890004568B1 publication Critical patent/KR890004568B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11803Masterslice integrated circuits using field effect technology
    • H01L27/11807CMOS gate arrays

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1019840003972A 1983-07-09 1984-07-09 마스터슬라이스형 반도체장치 KR890004568B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP58125288A JPS6017930A (ja) 1983-07-09 1983-07-09 マスタ・スライス方式に於ける基本セル
JP58125289A JPS6017931A (ja) 1983-07-09 1983-07-09 マスタ・スライス方式に於ける基本セル
JP125288,125289 1983-07-09

Publications (2)

Publication Number Publication Date
KR850000796A true KR850000796A (ko) 1985-03-09
KR890004568B1 KR890004568B1 (ko) 1989-11-15

Family

ID=26461759

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840003972A KR890004568B1 (ko) 1983-07-09 1984-07-09 마스터슬라이스형 반도체장치

Country Status (4)

Country Link
US (1) US4816887A (ko)
EP (1) EP0131463B1 (ko)
KR (1) KR890004568B1 (ko)
DE (1) DE3477312D1 (ko)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0695570B2 (ja) * 1985-02-07 1994-11-24 三菱電機株式会社 半導体集積回路装置
EP0224887B1 (de) * 1985-12-06 1992-03-11 Siemens Aktiengesellschaft Gate Array Anordnung in CMOS-Technik
DE3850790T2 (de) * 1987-02-09 1994-12-22 Fujitsu Ltd Gatematrix mit in Verbindungsgebiet begrabenem Transistor.
JPS6412577A (en) * 1987-07-06 1989-01-17 Canon Kk Thin film transistor
JPH0194636A (ja) * 1987-10-06 1989-04-13 Hitachi Ltd 半導体装置
EP0394598B1 (en) * 1989-04-28 1996-03-06 International Business Machines Corporation An improved gate array cell having FETS of different and optimized sizes
JPH0383375A (ja) * 1989-08-25 1991-04-09 Sony Corp 半導体装置
JPH03234059A (ja) * 1990-02-09 1991-10-18 Sony Corp 半導体メモリ
US5289021A (en) * 1990-05-15 1994-02-22 Siarc Basic cell architecture for mask programmable gate array with 3 or more size transistors
US5055716A (en) * 1990-05-15 1991-10-08 Siarc Basic cell for bicmos gate array
WO1992002957A1 (en) * 1990-08-10 1992-02-20 Seiko Epson Corporation Semiconductor device
JP3038939B2 (ja) * 1991-02-08 2000-05-08 日産自動車株式会社 半導体装置
US5440153A (en) * 1994-04-01 1995-08-08 United Technologies Corporation Array architecture with enhanced routing for linear asics
US5552333A (en) * 1994-09-16 1996-09-03 Lsi Logic Corporation Method for designing low profile variable width input/output cells
US5723883A (en) * 1995-11-14 1998-03-03 In-Chip Gate array cell architecture and routing scheme
US5698873A (en) * 1996-03-08 1997-12-16 Lsi Logic Corporation High density gate array base cell architecture
JP3152635B2 (ja) * 1996-09-09 2001-04-03 三洋電機株式会社 マスタスライス方式の基本セル、半導体集積回路装置、フリップフロップ回路、排他的論理和回路、マルチプレクサ及び加算器
US6445049B1 (en) * 1997-06-30 2002-09-03 Artisan Components, Inc. Cell based array comprising logic, transfer and drive cells
US6974978B1 (en) * 1999-03-04 2005-12-13 Intel Corporation Gate array architecture
JP3647323B2 (ja) * 1999-07-30 2005-05-11 富士通株式会社 半導体集積回路
US6617621B1 (en) 2000-06-06 2003-09-09 Virage Logic Corporation Gate array architecture using elevated metal levels for customization
JP2006156929A (ja) * 2004-04-19 2006-06-15 Fujitsu Ltd 半導体集積回路及びその設計方法
US8533641B2 (en) 2011-10-07 2013-09-10 Baysand Inc. Gate array architecture with multiple programmable regions

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
JPS5864047A (ja) * 1981-10-13 1983-04-16 Nec Corp マスタ−スライス半導体集積回路装置
JPS5897847A (ja) * 1981-12-08 1983-06-10 Nec Corp 集積回路装置
JPS58139446A (ja) * 1982-02-15 1983-08-18 Nec Corp 半導体集積回路装置
US4513307A (en) * 1982-05-05 1985-04-23 Rockwell International Corporation CMOS/SOS transistor gate array apparatus

Also Published As

Publication number Publication date
EP0131463A2 (en) 1985-01-16
EP0131463A3 (en) 1986-04-09
KR890004568B1 (ko) 1989-11-15
DE3477312D1 (de) 1989-04-20
US4816887A (en) 1989-03-28
EP0131463B1 (en) 1989-03-15

Similar Documents

Publication Publication Date Title
KR850000796A (ko) 마스터슬라이스형 반도체장치
EP0170052A3 (en) Master slice type semiconductor circuit device
DK165740C (da) Fluorsubstituerede phenoxyphenoxyalkoholer
DE3485409D1 (de) Halbleiterschaltvorrichtung.
KR900008928A (ko) 반도체 집적회로
DE3473973D1 (de) Masterslice semiconductor device
KR850001613A (ko) 반도체 메모리
KR850006779A (ko) 반도체 장치
IT1176163B (it) Dispositivo assortitore
DE3380383D1 (en) Master slice semiconductor device
DE3486418D1 (de) Halbleiterspeicheranordnung
DE3484817D1 (de) Halbleiteranordnung.
KR860004470A (ko) 반도체 장치
KR840005919A (ko) 반도체 장치
SE8305455L (sv) Spolningsanordning
KR850002673A (ko) 반도체장치 제조방법
IT8324175A1 (it) Dispositivo semiconduttore
IT8423942A0 (it) Dispositivo semiconduttore.
BR8305291A (pt) Dispositivo anti-ofuscante
IT1176548B (it) Dispositivo addolcitore per lavastoviglie
KR850000462U (ko) 조작장치
KR860005452A (ko) 반도체장치
KR860005449A (ko) 반도체장치
IT1175484B (it) Dispositivo di taglio
KR860004472A (ko) 반도체장치

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20031106

Year of fee payment: 15

EXPY Expiration of term