KR920008920A - 반도체 기판의 전압 레벨 요동을 방지하기 위한 반도체 집적회로의 출력 유닛 - Google Patents

반도체 기판의 전압 레벨 요동을 방지하기 위한 반도체 집적회로의 출력 유닛 Download PDF

Info

Publication number
KR920008920A
KR920008920A KR1019910018165A KR910018165A KR920008920A KR 920008920 A KR920008920 A KR 920008920A KR 1019910018165 A KR1019910018165 A KR 1019910018165A KR 910018165 A KR910018165 A KR 910018165A KR 920008920 A KR920008920 A KR 920008920A
Authority
KR
South Korea
Prior art keywords
semiconductor substrate
integrated circuit
output unit
voltage level
level fluctuation
Prior art date
Application number
KR1019910018165A
Other languages
English (en)
Other versions
KR950008449B1 (ko
Inventor
히데오 이나바
Original Assignee
세끼모또 다다히로
니뽄 덴끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세끼모또 다다히로, 니뽄 덴끼 가부시끼가이샤 filed Critical 세끼모또 다다히로
Publication of KR920008920A publication Critical patent/KR920008920A/ko
Application granted granted Critical
Publication of KR950008449B1 publication Critical patent/KR950008449B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

내용 없음

Description

반도체 기판의 전압 레벨 요동을 방지하기 위한 반도체 집적회로의 출력 유닛
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 반도체 메모리 장치에 구비된 본 발명에 따른 출력 유닛의 회로 구성을 도시한 회로도.

Claims (1)

  1. a) 각각 제1채널 도전형의 제1 트랜지스터(Qp11)와, 제1전압선(Vdd)과 상기 반도체 기판에 전기적으로 접속된 제2전압선(GND)사이에 접속된 공통 절점(N11) 및 제2채널 도전형의 제2트랜지스터(Qn12)로 구성된 복수의 출력 반전회로(141, 142, 14n)와; b) 각각 상기 공통 절점들의 하나와 접속되는 복수의 출력 데이타핀(OUT11, OUT12, OUTn)을, 구비하는, 단일한 반도체 기판(11)상에 형성된 집적회로의 출력 유닛에 있어서, c) 상기 제2전압선과 상기 반도체 기판사이에 접속된 저항 수단(R12)을, 더 포함하는 것을 특징으로 하는 출력 유닛.
    ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.
KR1019910018165A 1990-10-18 1991-10-16 반도체 기판의 전압 레벨 변동을 방지하기 위한 반도체 집적회로의 출력 유닛 KR950008449B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2279752A JPH04155693A (ja) 1990-10-18 1990-10-18 半導体記憶装置のデータ出力回路
JP90-279752 1990-10-18

Publications (2)

Publication Number Publication Date
KR920008920A true KR920008920A (ko) 1992-05-28
KR950008449B1 KR950008449B1 (ko) 1995-07-31

Family

ID=17615415

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910018165A KR950008449B1 (ko) 1990-10-18 1991-10-16 반도체 기판의 전압 레벨 변동을 방지하기 위한 반도체 집적회로의 출력 유닛

Country Status (5)

Country Link
US (1) US5357461A (ko)
EP (1) EP0481678B1 (ko)
JP (1) JPH04155693A (ko)
KR (1) KR950008449B1 (ko)
DE (1) DE69122203T2 (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0583696A (ja) * 1991-06-07 1993-04-02 Sony Corp 画像符号化装置
JPH05236427A (ja) * 1992-02-25 1993-09-10 Sony Corp 画像信号の符号化装置及び符号化方法
US5311083A (en) * 1993-01-25 1994-05-10 Standard Microsystems Corporation Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads
DE69705217T2 (de) * 1997-08-07 2001-09-20 St Microelectronics Srl Integrierte Anordnung für Schaltsysteme mit gefilterten Bezugsgrössen

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4376986A (en) * 1981-09-30 1983-03-15 Burroughs Corporation Double Lambda diode memory cell
JPS5921128A (ja) * 1982-07-26 1984-02-03 Nec Ic Microcomput Syst Ltd 電界効果半導体装置
JPH0714051B2 (ja) * 1986-07-15 1995-02-15 沖電気工業株式会社 半導体装置
US4797804A (en) * 1987-03-09 1989-01-10 International Business Machines Corporation High density, high performance, single event upset immune data storage cell
US4862018A (en) * 1987-11-30 1989-08-29 Texas Instruments Incorporated Noise reduction for output drivers
JP2822391B2 (ja) * 1988-06-27 1998-11-11 日本電気株式会社 半導体記憶装置
JP2855701B2 (ja) * 1989-09-29 1999-02-10 日本電気株式会社 Ｃｍｏｓ半導体集積回路装置

Also Published As

Publication number Publication date
US5357461A (en) 1994-10-18
JPH04155693A (ja) 1992-05-28
DE69122203D1 (de) 1996-10-24
EP0481678B1 (en) 1996-09-18
DE69122203T2 (de) 1997-01-30
KR950008449B1 (ko) 1995-07-31
EP0481678A1 (en) 1992-04-22

Similar Documents

Publication Publication Date Title
KR890008849A (ko) 퓨우즈 상태 검출회로
KR880003330A (ko) 내부회로의 동작모드를 스위치하기 위한 기능을 갖는 반도체집적회로
KR910019343A (ko) 입력회로
KR930008868A (ko) 시험회로를 내장한 기억용 반도체 집적회로
KR920022678A (ko) 반도체 메모리 장치의 데이타 입력버퍼
KR890017875A (ko) 마스터-슬레이브 플립플롭회로
KR870002653A (ko) 래치 엎 현상을 감소시키는 상보형 반도체장치
KR930020447A (ko) 반도체 메모리 장치의 비트라인 프리차아지방식
KR910002116A (ko) 반도체 장치를 위한 전압 발생회로
KR890013880A (ko) 지연회로
KR960035626A (ko) 파워 온 리셋 회로
KR910016077A (ko) 반도체집적회로
KR900001026A (ko) 반도체회로 및 그것을 사용한 신호처리 시스템
KR920001523A (ko) 검출 회로를 포함하는 반도체 집적회로
KR920008920A (ko) 반도체 기판의 전압 레벨 요동을 방지하기 위한 반도체 집적회로의 출력 유닛
KR940020669A (ko) 바이어스 회로(bias circuit)
KR910020896A (ko) 반도체집적회로
KR970024162A (ko) 풀업 또는 풀다운 저항을 갖는 반도체 장치(a semiconductor device having pull-up or pull-down resistance)
KR930006875A (ko) 집적회로
KR920017365A (ko) 반도체 집적회로
KR910014944A (ko) 반도체 집적회로장치
KR960027331A (ko) 버퍼회로 및 바이어스회로
KR880005743A (ko) 비교기
KR910020734A (ko) 스태틱형 반도체메모리
KR930005199A (ko) 반도체 기억장치

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010725

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee