KR900005452A - 반도체 메모리 - Google Patents
반도체 메모리 Download PDFInfo
- Publication number
- KR900005452A KR900005452A KR1019890013284A KR890013284A KR900005452A KR 900005452 A KR900005452 A KR 900005452A KR 1019890013284 A KR1019890013284 A KR 1019890013284A KR 890013284 A KR890013284 A KR 890013284A KR 900005452 A KR900005452 A KR 900005452A
- Authority
- KR
- South Korea
- Prior art keywords
- well
- independent
- wells
- rows
- cell array
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 8
- 239000000758 substrate Substances 0.000 claims 3
- 230000003068 static effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/83—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
- G11C29/832—Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도내지 제6도는 본 발명에 따른 반도체메모리의 각 실시예를 나타낸 구성설명도,
제7도는 제1도에 도시된 메모리셀어레이에서 2행마다 웰을 독립시킨 경우 일부의 메모리셀에 대한 평면 패턴예를 나타낸 회로도.
Claims (2)
- n행×m열의 스태틱메모리셀어레이를 갖추고 있는 반도체 메모리에 있어서, 상기 각 메모리셀에서 반도체기판과는 역도전형인 웰(105)이 상기 메모리셀어레이에서의 각 행 또는 복수행마다 독립되어 있으면서, 이 웰(105)은 그 웰상에 형성되어 있는 트랜지스트(T3,T4)의 소오스에 접속되어 있고, 이 웰(105)상에 형성되어 있는 각 트랜지스터의 소오스는 상기 독립된 웰마다 공통인 공통 소오스배선(1)에 접속되어있으며, 이 독립된 웰마다의 상기 공통 소오스배선(1)과 소오스전원전위가 선택적으로 스위치수단(SW1,SW1′)을 매개해서 접속되어 있는 것을 특징으로 하는 반도체메모리.
- n행×m열의 스태틱메모리셀어레이를 갖춘 반도체 메모리에 있어서, 상기 각 메모리셀에서 반도체기판과는 역도전형인 웰(31)이 상기 메모리셀어레이에서의 각 행 또는 복수행마다 독립되어 있으면서, 이 웰(31)은 그 웰상에 형성되어 있는 트랜지스트(T1,T2)의 소오스에 접속되어 있고, 이 웰(31)상에 형성되어 있는 각 트랜지스터(T1,T2)의 소오스는 상기 독립된 웰마다 공통인 공통 소오스배선(2)에 접속되어있으며, 이 독립된 웰마다의 상기 공통 소오스배선(2)과 소오스 전원전위 또는 상기 반도체기판과 동일한 전위로 절환접속시키기 위한 절환스위치회로(SW2,SW2')가 설치되어 있는 것을 특징으로 하는 반도체메모리.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63228058A JPH0682807B2 (ja) | 1988-09-12 | 1988-09-12 | 半導体メモリ |
JP63-228058 | 1988-09-12 | ||
JP88-228058 | 1988-09-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900005452A true KR900005452A (ko) | 1990-04-14 |
KR930004710B1 KR930004710B1 (ko) | 1993-06-03 |
Family
ID=16870535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019890013284A KR930004710B1 (ko) | 1988-09-12 | 1989-09-12 | 반도체 메모리 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5097448A (ko) |
EP (1) | EP0359204B1 (ko) |
JP (1) | JPH0682807B2 (ko) |
KR (1) | KR930004710B1 (ko) |
DE (1) | DE68925087T2 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03245400A (ja) * | 1990-02-21 | 1991-10-31 | Mitsubishi Electric Corp | 半導体メモリ装置 |
JP2782948B2 (ja) * | 1990-11-16 | 1998-08-06 | 日本電気株式会社 | 半導体メモリ |
US5446310A (en) * | 1992-06-08 | 1995-08-29 | North Carolina State University | Integrated circuit power device with external disabling of defective devices and method of fabricating same |
US5392187A (en) * | 1992-08-12 | 1995-02-21 | North Carolina State University At Raleigh | Integrated circuit power device with transient responsive current limiting means |
JP3354231B2 (ja) * | 1993-09-29 | 2002-12-09 | 三菱電機エンジニアリング株式会社 | 半導体装置 |
US6750107B1 (en) * | 1996-01-31 | 2004-06-15 | Micron Technology, Inc. | Method and apparatus for isolating a SRAM cell |
DE69727581D1 (de) * | 1997-11-28 | 2004-03-18 | St Microelectronics Srl | RAM-Speicherzelle mit niedriger Leistungsaufnahme |
EP1252654B1 (en) | 2000-01-28 | 2007-08-08 | Interuniversitair Micro-Elektronica Centrum Vzw | A method for transferring and stacking of semiconductor devices |
JP4530527B2 (ja) * | 2000-12-08 | 2010-08-25 | ルネサスエレクトロニクス株式会社 | スタティック型半導体記憶装置 |
US7437632B2 (en) * | 2003-06-24 | 2008-10-14 | Micron Technology, Inc. | Circuits and methods for repairing defects in memory devices |
TW201029012A (en) * | 2009-01-23 | 2010-08-01 | Nanya Technology Corp | Operation method of suppressing current leakage in a memory and access method for the same |
JP5143179B2 (ja) * | 2010-04-16 | 2013-02-13 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5472691A (en) * | 1977-11-21 | 1979-06-11 | Toshiba Corp | Semiconductor device |
JPS58208998A (ja) * | 1982-05-28 | 1983-12-05 | Toshiba Corp | 半導体cmosメモリ |
US4587638A (en) * | 1983-07-13 | 1986-05-06 | Micro-Computer Engineering Corporation | Semiconductor memory device |
EP0186175A3 (en) * | 1984-12-24 | 1989-02-08 | Nec Corporation | Semiconductor memory device having improved redundant structure |
US4731759A (en) * | 1985-03-18 | 1988-03-15 | Nec Corporation | Integrated circuit with built-in indicator of internal repair |
US4685086A (en) * | 1985-11-14 | 1987-08-04 | Thomson Components-Mostek Corp. | Memory cell leakage detection circuit |
US4858182A (en) * | 1986-12-19 | 1989-08-15 | Texas Instruments Incorporated | High speed zero power reset circuit for CMOS memory cells |
-
1988
- 1988-09-12 JP JP63228058A patent/JPH0682807B2/ja not_active Expired - Lifetime
-
1989
- 1989-09-11 US US07/405,885 patent/US5097448A/en not_active Expired - Lifetime
- 1989-09-12 EP EP89116872A patent/EP0359204B1/en not_active Expired - Lifetime
- 1989-09-12 KR KR1019890013284A patent/KR930004710B1/ko not_active IP Right Cessation
- 1989-09-12 DE DE68925087T patent/DE68925087T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US5097448A (en) | 1992-03-17 |
EP0359204A3 (en) | 1991-08-28 |
DE68925087T2 (de) | 1996-05-30 |
EP0359204A2 (en) | 1990-03-21 |
EP0359204B1 (en) | 1995-12-13 |
JPH0276244A (ja) | 1990-03-15 |
DE68925087D1 (de) | 1996-01-25 |
KR930004710B1 (ko) | 1993-06-03 |
JPH0682807B2 (ja) | 1994-10-19 |
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