JPS5644191A - Semiconductor memory cell circuit - Google Patents

Semiconductor memory cell circuit

Info

Publication number
JPS5644191A
JPS5644191A JP11840279A JP11840279A JPS5644191A JP S5644191 A JPS5644191 A JP S5644191A JP 11840279 A JP11840279 A JP 11840279A JP 11840279 A JP11840279 A JP 11840279A JP S5644191 A JPS5644191 A JP S5644191A
Authority
JP
Japan
Prior art keywords
memory cell
transistors
circuit
wiring
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11840279A
Other languages
Japanese (ja)
Inventor
Masahiro Mikami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP11840279A priority Critical patent/JPS5644191A/en
Publication of JPS5644191A publication Critical patent/JPS5644191A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To reduce the area of a memory cell and to reduce the number of wiring by providing a multistable circuit made of MOS transistors and by constituting a selecting circuit that couples the circuit with bit lines. CONSTITUTION:Diode 17 is that consisting of diffused area 38 of PMOS transistor 18 and N wafer 28, and diode 25 is that consisting of diffused area 37 of NMOS transistor 16 and substrate 20. Diodes 17 and 25 are reversely biased and when transistors 16 and 18 are both OFF, node 19 stays at a low voltage (close to that of the substrate). Since that circuit is symmetric, diodes 23 and 26 and node 22 are the same. This memory cell used four transistors and its number of wiring is 3.5, which results in that two transistors and a half wiring are saved in comparison with the conventional cell.
JP11840279A 1979-09-14 1979-09-14 Semiconductor memory cell circuit Pending JPS5644191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11840279A JPS5644191A (en) 1979-09-14 1979-09-14 Semiconductor memory cell circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11840279A JPS5644191A (en) 1979-09-14 1979-09-14 Semiconductor memory cell circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP62066472A Division JPS62283494A (en) 1987-03-20 1987-03-20 Semiconductor memory cell circuit

Publications (1)

Publication Number Publication Date
JPS5644191A true JPS5644191A (en) 1981-04-23

Family

ID=14735759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11840279A Pending JPS5644191A (en) 1979-09-14 1979-09-14 Semiconductor memory cell circuit

Country Status (1)

Country Link
JP (1) JPS5644191A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6090279A (en) * 1983-10-24 1985-05-21 Sumitomo Naugatuck Co Ltd Adhesive for carpet backing
JP2007122818A (en) * 2005-10-28 2007-05-17 Toshiba Corp Semiconductor memory device and semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368991A (en) * 1976-12-02 1978-06-19 Fujitsu Ltd 4-transistor static memory cell

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5368991A (en) * 1976-12-02 1978-06-19 Fujitsu Ltd 4-transistor static memory cell

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6090279A (en) * 1983-10-24 1985-05-21 Sumitomo Naugatuck Co Ltd Adhesive for carpet backing
JP2007122818A (en) * 2005-10-28 2007-05-17 Toshiba Corp Semiconductor memory device and semiconductor device

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