KR890016623A - 반도체 집적회로 장치 - Google Patents

반도체 집적회로 장치 Download PDF

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Publication number
KR890016623A
KR890016623A KR1019890005434A KR890005434A KR890016623A KR 890016623 A KR890016623 A KR 890016623A KR 1019890005434 A KR1019890005434 A KR 1019890005434A KR 890005434 A KR890005434 A KR 890005434A KR 890016623 A KR890016623 A KR 890016623A
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KR
South Korea
Prior art keywords
gate cell
common wiring
integrated circuit
circuit device
logic
Prior art date
Application number
KR1019890005434A
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English (en)
Inventor
야스오 사또
도오루 고바야시
Original Assignee
미다 가쓰시게
가부시끼가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 미다 가쓰시게, 가부시끼가이샤 히다찌세이사꾸쇼 filed Critical 미다 가쓰시게
Publication of KR890016623A publication Critical patent/KR890016623A/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1735Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118Masterslice integrated circuits
    • H01L27/11801Masterslice integrated circuits using bipolar technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음

Description

반도체 집적회로 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도는 본 발명이 적용된 고속디지탈 처리장치의 1실시예를 도시한 배면도. 제 2 도는 제 1 도의 고속디지탈 처리장치의 1실시예를 도시한 부분적인 회로도. 제 3 도는 본 발명이 적용된 고속디지탈 처리장치의 다른 실시예를 도시한 배치도.

Claims (4)

  1. 제 1 의 논리게이트셀군, 상기 제 1 의 논리게이트셀군내의 각 논리게이트셀의 출력단자를 결합하기 위해 각 출력단자와 근접하도록 직렬형상으로 배치된 제 1 의 공통배선, 상기 제 1 의 공통 배선의 한쪽끝에 결합되는 논리게이트셀내에 마련되고, 상기 제 1 의 논리게이트셀군내의 각 논리 게이트셀에 대해서 공통으로 사용되는 출력레벨 설정용 종단저항, 제 2 의 놀리게이트셀군 및 상기 제 2 의 논리게이트셀군내의 각 놀리게이트셀의 입력 단자와 상기 제 1 의 공통배선의 다른쪽 결합하기 위한 제 2 의 공통배선을 포함하는 반도체 집적회로 장치.
  2. 특허청구의 범위 제 1 항에 있어서, 상기 각 논리게이트셀은 이미터 결합논리회로 및 그 이미터가 상기 각 출력단자에 결합되는 이미터 출력 트랜지스터를 포함하는 반도체 집적회로 장치.
  3. 특허청구의 범위 제 2 항에 있어서, 상기 제 1 의 논리게이트셀군내의 논리게이트셀중 상기 제 1 의 공통배선의 한쪽끝에 결합된 논리게이트셀의 이미터 출력드랜지스터에는 상기 종단저항이 이미터저항으로서 접속되고, 다른 논리게이트셀의 이미터 출력트랜지스터는 오픈이미터형으로 되는 반도체집적회로 장치.
  4. 특허청구의 범위 제 3 항에 있어서, 상기 반도체 직접회로 장치는 게이트 어레이 집적회로 장치이고, 상기 제 1 의 공통배선과 상기 제 2 의 공통배선은 논리게이트셀을 거쳐서 결합되는 반도체 집적회로 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890005434A 1988-04-30 1989-04-25 반도체 집적회로 장치 KR890016623A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63107818A JPH01278041A (ja) 1988-04-30 1988-04-30 半導体集積回路装置
JP63-107818 1988-04-30

Publications (1)

Publication Number Publication Date
KR890016623A true KR890016623A (ko) 1989-11-29

Family

ID=14468813

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890005434A KR890016623A (ko) 1988-04-30 1989-04-25 반도체 집적회로 장치

Country Status (3)

Country Link
US (1) US4987326A (ko)
JP (1) JPH01278041A (ko)
KR (1) KR890016623A (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130578A (en) * 1989-11-30 1992-07-14 Hughes Aircraft Company Efficient high speed N-word comparator
US5338982A (en) * 1991-03-29 1994-08-16 Kawasaki Steel Corporation Programmable logic device
US5510733A (en) * 1994-12-23 1996-04-23 Sun Microsystems, Inc. High speed circuit with CMOS and bipolar logic stages
JP2001051957A (ja) * 1999-08-04 2001-02-23 Hitachi Ltd オンチップマルチプロセッサ

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4207556A (en) * 1976-12-14 1980-06-10 Nippon Telegraph And Telephone Public Corporation Programmable logic array arrangement
JPS60953B2 (ja) * 1977-12-30 1985-01-11 富士通株式会社 半導体集積回路装置
JPH077825B2 (ja) * 1981-08-13 1995-01-30 富士通株式会社 ゲートアレイの製造方法
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates
JPS6074455A (ja) * 1983-09-29 1985-04-26 Fujitsu Ltd マスタスライス集積回路
US4751406A (en) * 1985-05-03 1988-06-14 Advanced Micro Devices, Inc. ECL circuit with output transistor auxiliary biasing circuit
US4849659A (en) * 1987-12-15 1989-07-18 North American Philips Corporation, Signetics Division Emitter-coupled logic circuit with three-state capability
US4804861A (en) * 1988-02-11 1989-02-14 Motorola, Inc. Multifunction onboard input/output termination

Also Published As

Publication number Publication date
US4987326A (en) 1991-01-22
JPH01278041A (ja) 1989-11-08

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