KR910007122A - 반도체 메모리 - Google Patents

반도체 메모리 Download PDF

Info

Publication number
KR910007122A
KR910007122A KR1019900014435A KR900014435A KR910007122A KR 910007122 A KR910007122 A KR 910007122A KR 1019900014435 A KR1019900014435 A KR 1019900014435A KR 900014435 A KR900014435 A KR 900014435A KR 910007122 A KR910007122 A KR 910007122A
Authority
KR
South Korea
Prior art keywords
memory
wirings
cells
semiconductor memory
semiconductor
Prior art date
Application number
KR1019900014435A
Other languages
English (en)
Other versions
KR930009020B1 (ko
Inventor
유타카 다나카
신스케 다카세
히사시 하시모토
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
다케다이 마사다카
도시바 마이크로일렉트로닉스 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바, 다케다이 마사다카, 도시바 마이크로일렉트로닉스 가부시키가이샤 filed Critical 아오이 죠이치
Publication of KR910007122A publication Critical patent/KR910007122A/ko
Application granted granted Critical
Publication of KR930009020B1 publication Critical patent/KR930009020B1/ko

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 메모리
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명에 따른 각 실시예의 패턴평면도.

Claims (5)

  1. 메모리셀이 형성되는 기본셀(111, 112, 113, 371, 372)내에 배선된 워드선(W′, 31, ℓ″, 32)이 워드선신호가 입력되는 트랜지스터의 게이트전극배선(W′, 31)및 금속배선 (ℓ″, 32)으로 이루어지고, 이들 양 배선의 접속용 관통구멍(121, 36)을 복수의 메모리셀에 대해 그 수 보다 적은 부분에 설치한 것을 특징으로 하는 반도체메모리.
  2. 제1항에 있어서, 상기 기본셀(111,112,113, 371,372)이 상기 메모리셀을 구성하는 것을 특징으로 하는 반도체메모리.
  3. 제1항에 있어서, 상기 양 배선의 접속용 관통구멍(121)을 메모리셀 바깥영역(21)에 설치하고, 이 메모리셀 바깥영역(21)내에 단결정반도체층과 다른 금속배선과의 접속용 관통구멍(122)을 설치한 것을 특징으로 하는 반도체메모리.
  4. 제1항 또는 제2항에 있어서, 상기 복수의 메모리셀은 기본셀내에 상기 양 배선간의 접속용 관통구멍(121, 36)을 갖는 것과 갖지 않은 것이 혼합된 것임을 특징으로 하는 반도체메모리.
  5. 제1항 또는 제4항에 있어서, 상기 복수의 메모리셀은 상기 금속배선과 단결정반도체층과의 사이에 접속용 관통구멍(122, 35)을 갖는 것과 갖지 않는 것이 혼합된 것임을 특징으로 하는 반도체메모리.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900014435A 1989-09-13 1990-09-13 반도체 메모리 KR930009020B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-237507 1989-09-13
JP23750789A JPH07114258B2 (ja) 1989-09-13 1989-09-13 半導体メモリ

Publications (2)

Publication Number Publication Date
KR910007122A true KR910007122A (ko) 1991-04-30
KR930009020B1 KR930009020B1 (ko) 1993-09-18

Family

ID=17016345

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900014435A KR930009020B1 (ko) 1989-09-13 1990-09-13 반도체 메모리

Country Status (5)

Country Link
US (1) US5698872A (ko)
EP (1) EP0421168B1 (ko)
JP (1) JPH07114258B2 (ko)
KR (1) KR930009020B1 (ko)
DE (1) DE69032419T2 (ko)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5410173A (en) * 1991-01-28 1995-04-25 Kikushima; Ken'ichi Semiconductor integrated circuit device
US5783849A (en) * 1996-02-23 1998-07-21 Citizen Watch Co., Ltd. Semiconductor device
KR100269297B1 (ko) * 1997-04-25 2000-12-01 윤종용 파워라인들과제어라인들을구비하는집적회로
US5864496A (en) * 1997-09-29 1999-01-26 Siemens Aktiengesellschaft High density semiconductor memory having diagonal bit lines and dual word lines
US6033955A (en) * 1998-09-23 2000-03-07 Advanced Micro Devices, Inc. Method of making flexibly partitioned metal line segments for a simultaneous operation flash memory device with a flexible bank partition architecture
JP2001344966A (ja) * 2000-06-06 2001-12-14 Toshiba Corp 半導体記憶装置
US6703641B2 (en) * 2001-11-16 2004-03-09 International Business Machines Corporation Structure for detecting charging effects in device processing
JP2004119937A (ja) * 2002-09-30 2004-04-15 Fujitsu Ltd 半導体記憶装置
US6927429B2 (en) * 2003-02-14 2005-08-09 Freescale Semiconductor, Inc. Integrated circuit well bias circuity
US7042030B2 (en) * 2003-11-21 2006-05-09 Texas Instruments Incorporated High density memory array

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4342100A (en) * 1979-01-08 1982-07-27 Texas Instruments Incorporated Implant programmable metal gate MOS read only memory
JPS5854654A (ja) * 1981-09-28 1983-03-31 Nec Corp 半導体集積回路装置
DE3380548D1 (en) * 1982-03-03 1989-10-12 Fujitsu Ltd A semiconductor memory device
JPS594159A (ja) * 1982-06-30 1984-01-10 Mitsubishi Electric Corp 半導体集積回路
JPS6030170A (ja) * 1983-07-29 1985-02-15 Hitachi Ltd 高集積読み出し専用メモリ
JPH0793364B2 (ja) * 1984-08-10 1995-10-09 株式会社日立製作所 半導体集積回路装置
US4679171A (en) * 1985-02-07 1987-07-07 Visic, Inc. MOS/CMOS memory cell
JPS61267347A (ja) * 1985-05-22 1986-11-26 Toshiba Corp 半導体装置
JPS62145862A (ja) * 1985-12-20 1987-06-29 Sanyo Electric Co Ltd 半導体記憶装置
JPS62169472A (ja) * 1986-01-22 1987-07-25 Hitachi Ltd 半導体集積回路装置
US4744056A (en) * 1986-02-28 1988-05-10 Advanced Micro Devices, Inc. Stable high density RAM
JPH01140741A (ja) * 1987-11-27 1989-06-01 Ricoh Co Ltd 半導体メモリ装置

Also Published As

Publication number Publication date
KR930009020B1 (ko) 1993-09-18
EP0421168A3 (en) 1994-07-13
JPH03101152A (ja) 1991-04-25
EP0421168B1 (en) 1998-06-17
DE69032419T2 (de) 1998-12-03
JPH07114258B2 (ja) 1995-12-06
EP0421168A2 (en) 1991-04-10
US5698872A (en) 1997-12-16
DE69032419D1 (de) 1998-07-23

Similar Documents

Publication Publication Date Title
KR850002670A (ko) 마스터 슬라이스 반도체 장치
KR840003146A (ko) 다이나믹(Dynamic) RAM 집적회로 장치
KR920020515A (ko) 반도체 판독전용메모리
KR900003889A (ko) 반도체 메모리회로
KR890004321A (ko) 로직마크로 및 랜덤억세스메모리 마크로를 구비한 반도체 집적회로장치
KR950034686A (ko) 게이트 어레이의 기본 셀 및 이 기본 셀을 포함하는 게이트 어레이
KR890016573A (ko) 반도체기억장치
KR910007122A (ko) 반도체 메모리
KR860002866A (ko) 반도체 집적회로장치
KR900010999A (ko) 반도체 장치
KR940008103A (ko) 반도체 독출전용 메모리
KR930024187A (ko) 시냅스 모스 트랜지스터
KR910001945A (ko) 반도체장치
KR850000799A (ko) 호출 전용 메모리
KR970017618A (ko) 반도체 메모리 장치
KR910008836A (ko) 반도체기억장치
KR920001708A (ko) 반도체 집적회로
KR920007178A (ko) 반도체 집적회로
KR910010688A (ko) 반도체장치
KR910010715A (ko) 반도체 메모리
KR880011804A (ko) 반도체 집적회로 장치
KR890007406A (ko) 고밀도 집적회로
KR890013771A (ko) 반도체장치
KR850002679A (ko) 대규모 집적회로 실장의 다중신호 경로 분배 시스템
EP0278587A3 (en) Memory cell

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090827

Year of fee payment: 17

EXPY Expiration of term