KR880011804A - 반도체 집적회로 장치 - Google Patents
반도체 집적회로 장치 Download PDFInfo
- Publication number
- KR880011804A KR880011804A KR1019880002817A KR880002817A KR880011804A KR 880011804 A KR880011804 A KR 880011804A KR 1019880002817 A KR1019880002817 A KR 1019880002817A KR 880002817 A KR880002817 A KR 880002817A KR 880011804 A KR880011804 A KR 880011804A
- Authority
- KR
- South Korea
- Prior art keywords
- word line
- integrated circuit
- semiconductor integrated
- circuit device
- memory cell
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims 9
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- 229910021332 silicide Inorganic materials 0.000 claims 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 claims 1
- 239000003990 capacitor Substances 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/911—Light sensitive array adapted to be scanned by electron beam, e.g. vidicon device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
내용없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예를 도시한 다이나믹형 RAM의 메모리어레이를 도시한 배치도
제2도는 본 발명이 적용된 다이나믹형 RAM의 1실시예를 도시한 회로블럭도
제4도는 제1도 및 제3도의 다이나믹형 RAM의 메모리어레이에 있어서의 A-B 단면도
Claims (9)
- 병행하여 배치되는 여러개의 데이터선, 상기 데이터선과 직교하고, 또한 각각이 병행하여 배치되는 여러개의 워드선, 상기 데이터선과 워드선의 교점에 격자형상으로 배치되고, 정보측정용 캐패시터와 어드레스 선택용 MOSFET로 되며, 또한 인접하는 워드선에 결합되는 1쌍의 메모리셀에 있어서, 그 어드레서스선택용 MOSFET의 드레인 영역이 공유되는 여러개쌍의 메모리셀, 상기 워드선과 병행하여 분단해서 배치되고, 대응하는 로우에 배치되는 여러개 메모리셀의 일부분의 어드레스 선택용 MOSFET 게이트가 결합되며, 또 각각이 대응하는 상기 워드선에 결합되는 여러개의 분할 워드선으로 된 반도체 집적회로 장치.
- 특허청구의 범위 제1항에 있어서, 상기 어드레스선택용 MOSFET의 드레인 영역을 공유하는 여러개쌍의 메모리셀중, 공유 드레인영역을 사이에 두고 한쪽에 배치되는 메모리셀과 다른쪽에 배치되는 메모리셀은 상기 인접하는 2줄의 워드선에 대하여 동수가 결합되는 반도체 집적회로장치.
- 특허청구의 범위 제1항에 있어서, 상기 분할워드선은 상기 워드선의 결합부에 있어서 교차되는 것에 의하여 상기 어드레스 선택용 MOSFET의 드레인 영역을 공유하는 여러개쌍의 메모리셀중, 공유드레인영역을 사이에 두고 한쪽에 배치되는 메모리셀과 다른 쪽에 배치되는 메모리셀이 상기 인접하는 2줄의 워드선에 대하여 동수가 결합되는 반도체 집적회로 장치.
- 특허 청구의 범위 제1항에 있어서, 상기 워드선은 알루미륨층의 의하여 형성되는 반도체 집적회로 장치.
- 특허청구의 범위 제1항에 있어서, 상기 분할 워드선은 다결성 실리콘층에 의하여 형성되는 반도체 집적회로 장치.
- 특허청구의 범위 제1항에 있어서, 상기 분할 워드선은 실리사이드층에 의하여 형성되는 반도체 집적회로 장치.
- 특허청구의 범위 제1항에 있어서, 상기 분할 워드선은 다결정 실리콘층과 실리사이드층으로 된 2층막에 의하여 형성되는 반도체 집적회로 장치.
- 특허청구의 범위 제1항에 있어서, 상기 워드선과 분할워드선에 결합부는 상기 메모리 셀상 또는 메모리셀 어레이상에 있는 반도체 집적회로 장치.
- 특허청구의 범위 제8항에 있어서, 상기 워드선과 분할 워드선의 결합부는 상기 메모리셀어레이 사이에 있는 반도체 집적회로 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-71429 | 1987-03-27 | ||
JP62071429A JPS63239674A (ja) | 1987-03-27 | 1987-03-27 | ダイナミツク型ram |
Publications (2)
Publication Number | Publication Date |
---|---|
KR880011804A true KR880011804A (ko) | 1988-10-31 |
KR960016426B1 KR960016426B1 (ko) | 1996-12-11 |
Family
ID=13460265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880002817A KR960016426B1 (ko) | 1987-03-27 | 1988-03-17 | 반도체 집적회로 장치 |
Country Status (3)
Country | Link |
---|---|
US (1) | US4967396A (ko) |
JP (1) | JPS63239674A (ko) |
KR (1) | KR960016426B1 (ko) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5251168A (en) * | 1991-07-31 | 1993-10-05 | Texas Instruments Incorporated | Boundary cells for improving retention time in memory devices |
US5875148A (en) * | 1993-01-29 | 1999-02-23 | Oki Electric Industry Co., Ltd. | Semiconductor memory |
US5864181A (en) | 1993-09-15 | 1999-01-26 | Micron Technology, Inc. | Bi-level digit line architecture for high density DRAMs |
US6043562A (en) * | 1996-01-26 | 2000-03-28 | Micron Technology, Inc. | Digit line architecture for dynamic memory |
US5875149A (en) * | 1997-02-06 | 1999-02-23 | Hyndai Electronics America | Word line driver for semiconductor memories |
US6011746A (en) * | 1997-02-06 | 2000-01-04 | Hyundai Electronics America, Inc. | Word line driver for semiconductor memories |
TW407234B (en) * | 1997-03-31 | 2000-10-01 | Hitachi Ltd | Semiconductor memory device, non-volatile semiconductor memory device and data reading method thereof |
US6570781B1 (en) | 2000-06-28 | 2003-05-27 | Marvell International Ltd. | Logic process DRAM |
US7184290B1 (en) | 2000-06-28 | 2007-02-27 | Marvell International Ltd. | Logic process DRAM |
US6947324B1 (en) | 2000-06-28 | 2005-09-20 | Marvell International Ltd. | Logic process DRAM |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5736844A (en) * | 1980-08-15 | 1982-02-27 | Hitachi Ltd | Semiconductor device |
JPS58111347A (ja) * | 1981-12-24 | 1983-07-02 | Matsushita Electric Ind Co Ltd | 半導体装置 |
DE3380548D1 (en) * | 1982-03-03 | 1989-10-12 | Fujitsu Ltd | A semiconductor memory device |
US4733374A (en) * | 1985-03-30 | 1988-03-22 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device |
-
1987
- 1987-03-27 JP JP62071429A patent/JPS63239674A/ja active Pending
-
1988
- 1988-03-17 KR KR1019880002817A patent/KR960016426B1/ko not_active IP Right Cessation
-
1990
- 1990-01-29 US US07/471,073 patent/US4967396A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR960016426B1 (ko) | 1996-12-11 |
US4967396A (en) | 1990-10-30 |
JPS63239674A (ja) | 1988-10-05 |
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