KR850006982A - 반도체 메모리 장치 - Google Patents

반도체 메모리 장치 Download PDF

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Publication number
KR850006982A
KR850006982A KR1019840007747A KR840007747A KR850006982A KR 850006982 A KR850006982 A KR 850006982A KR 1019840007747 A KR1019840007747 A KR 1019840007747A KR 840007747 A KR840007747 A KR 840007747A KR 850006982 A KR850006982 A KR 850006982A
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South Korea
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KR1019840007747A
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KR890004768B1 (ko
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야스오 이도우
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사바 쇼오이찌
가부시기 가이샤 도오시바
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음

Description

반도체 메모리 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 트랜지스터와 1캐퍼시터에서 이루어진 메모리셀을 나타내는 회로도. 제2도는 상기 메모리셀을 배열한 메모리어레이를 나타내는 회로도. 제5도는 본 발명의 일실시예에 메모리어레이를 나타내는 평면도.
1-MOSFET, 2-MOS캐퍼시터, WL,WLi-워드선, Wij -메모리셀, BL,BLj-비드선, 31-Si기판, 32,34-절연막, 33-제1 워드선, 35-제2 워드선, 41-일점쇄선, 42,61-실선, 51-P형 Si-기판, 52-필드산화막, 53-n-층, 541,542-게이트산화막, 55-OS캐퍼시터전극(제1 층다결정실리콘막), 56-제1 워드선겸 게이트 전극(제2층 다결정실리콘막),56-워드선, 57-n+층(소오스, 드레인), 581,582-CVD산화막, 59-비드선(제1층 Al막), 599-스페샤(Spacer)막 (제1층 Al막), 60-제2워드선(제2층 Al막), 62-파선 C1∼C8, C11∼C18-접촉위치.

Claims (4)

  1. 반도체기판상에다 매트릭스로 배열하여 형성되는 복수 메모리셀과 상기 메모리셀을 선택적으로 구동시키는 각각 복수개로된 행어드레스선 및 열어드래스선을 갖는 반도체메모리 장치에 있어서, 상기 열어드레스선에는 열위에 있는 전체메모리셀의 게이트 전극으로 접속되는 제1 열어드레스선, 상기 제1 열어드레스선위에 절연막을 매개해서 적층되므로서 제1 열어드레스선에 대해 부등간격을 두고 복수개소로 접촉하는 제2 열어드레스선으로 구성된 것을 특징으로 하는 반도체 메모리 장치.
  2. 제1항에 있어서, 상기 제1 열어드레스선과 제2 열어드레스선의 접촉위치 배열이 열어드레스선 구동 회로로 부터 떨어짐에 따라 핏치가 적게되어 부등간격로으 배열된 것.
  3. 제1항에 있어서, 상기 메모리셀이 1개의 캐퍼시터와 1개의 MOSFET로 구성되고, 상기 열어드레스 선이 MOSFET의 게이트전극에 접속되는 것으로써 상기 제1 열어드레스선을 MOSFET의 게이트전극과 일체적으로 하여 다결정실리콘막에 의해 형성된 것.
  4. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840007747A 1984-03-30 1984-12-07 반도체 메모리장치 KR890004768B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59-62730 1984-03-30
JP59062730A JPS60206164A (ja) 1984-03-30 1984-03-30 半導体メモリ装置

Publications (2)

Publication Number Publication Date
KR850006982A true KR850006982A (ko) 1985-10-25
KR890004768B1 KR890004768B1 (ko) 1989-11-25

Family

ID=13208774

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Application Number Title Priority Date Filing Date
KR1019840007747A KR890004768B1 (ko) 1984-03-30 1984-12-07 반도체 메모리장치

Country Status (5)

Country Link
US (1) US4638458A (ko)
EP (1) EP0160392B1 (ko)
JP (1) JPS60206164A (ko)
KR (1) KR890004768B1 (ko)
DE (1) DE3564516D1 (ko)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0793369B2 (ja) * 1985-06-26 1995-10-09 株式会社日立製作所 半導体記憶装置
US4800530A (en) * 1986-08-19 1989-01-24 Kabushiki Kasiha Toshiba Semiconductor memory system with dynamic random access memory cells
JP2584986B2 (ja) * 1987-03-10 1997-02-26 三菱電機株式会社 半導体装置の配線構造
JP2569040B2 (ja) * 1987-03-18 1997-01-08 株式会社日立製作所 半導体集積回路装置
JPH07120770B2 (ja) * 1987-07-03 1995-12-20 キヤノン株式会社 光電変換装置
US5204842A (en) * 1987-08-05 1993-04-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory with memory unit comprising a plurality of memory blocks
JP2847727B2 (ja) * 1988-12-27 1999-01-20 日本電気株式会社 半導体装置
JPH03166762A (ja) * 1989-11-27 1991-07-18 Sony Corp 半導体メモリ
US5760452A (en) * 1991-08-22 1998-06-02 Nec Corporation Semiconductor memory and method of fabricating the same
US5671397A (en) 1993-12-27 1997-09-23 At&T Global Information Solutions Company Sea-of-cells array of transistors
US6675361B1 (en) 1993-12-27 2004-01-06 Hyundai Electronics America Method of constructing an integrated circuit comprising an embedded macro
JPH07244983A (ja) * 1994-02-28 1995-09-19 Nec Corp 半導体記憶装置
JPH08148656A (ja) * 1994-11-22 1996-06-07 Nec Corp 半導体メモリ
JP3352851B2 (ja) * 1995-07-31 2002-12-03 株式会社東芝 半導体集積回路装置の配線方法
US5712510A (en) * 1995-08-04 1998-01-27 Advanced Micro Devices, Inc. Reduced electromigration interconnection line
US5689139A (en) * 1995-09-11 1997-11-18 Advanced Micro Devices, Inc. Enhanced electromigration lifetime of metal interconnection lines
EP0953983A3 (en) * 1996-03-01 2005-10-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with clamping circuit for preventing malfunction
DE69700241T2 (de) * 1996-03-01 1999-11-04 Mitsubishi Electric Corp Halbleiterspeichergerät, um Fehlfunktion durch Zeilenauswahlleitungsunterbrechung zu vermeiden
US6134144A (en) * 1997-09-19 2000-10-17 Integrated Memory Technologies, Inc. Flash memory array
US5864496A (en) * 1997-09-29 1999-01-26 Siemens Aktiengesellschaft High density semiconductor memory having diagonal bit lines and dual word lines
CN1315189C (zh) * 2003-05-06 2007-05-09 旺宏电子股份有限公司 字符线交接点布局结构
JP4819548B2 (ja) 2006-03-30 2011-11-24 富士通セミコンダクター株式会社 半導体装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54110068U (ko) * 1978-01-20 1979-08-02
JPS5598852A (en) * 1979-01-23 1980-07-28 Nec Corp Memory device
JPS58199557A (ja) * 1982-05-15 1983-11-19 Toshiba Corp ダイナミツクメモリ装置
JPS58213450A (ja) * 1982-06-04 1983-12-12 Toshiba Corp 半導体装置の多層配線構造

Also Published As

Publication number Publication date
KR890004768B1 (ko) 1989-11-25
JPH0360182B2 (ko) 1991-09-12
EP0160392A2 (en) 1985-11-06
DE3564516D1 (en) 1988-09-22
US4638458A (en) 1987-01-20
JPS60206164A (ja) 1985-10-17
EP0160392B1 (en) 1988-08-17
EP0160392A3 (en) 1985-12-27

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