KR910013555A - 반도체 기억장치 - Google Patents

반도체 기억장치 Download PDF

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Publication number
KR910013555A
KR910013555A KR1019900017847A KR900017847A KR910013555A KR 910013555 A KR910013555 A KR 910013555A KR 1019900017847 A KR1019900017847 A KR 1019900017847A KR 900017847 A KR900017847 A KR 900017847A KR 910013555 A KR910013555 A KR 910013555A
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KR
South Korea
Prior art keywords
capacitor
electrode layer
lines
semiconductor substrate
switching element
Prior art date
Application number
KR1019900017847A
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English (en)
Other versions
KR950010393B1 (ko
Inventor
가즈다리 아리모도
Original Assignee
시기 모리야
미쓰비시 뎅끼 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 시기 모리야, 미쓰비시 뎅끼 가부시끼가이샤 filed Critical 시기 모리야
Publication of KR910013555A publication Critical patent/KR910013555A/ko
Application granted granted Critical
Publication of KR950010393B1 publication Critical patent/KR950010393B1/ko

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음.

Description

반도체 기억장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명의 제1의 실시예에 의한 DRAM의 메모리셀 어레이의 평면 구조도,
제2도는, 제1도중의 절단선 II-II에 따른 방향으로부터의 단면 구조도.

Claims (1)

  1. 한개의 스위칭소자와 한개의 커패시터로 이루어지는 단위에모리셀을 복수개 배열한 기억영역을 가지는 반도체 기억장치이고, 주표면을 가지는 제1도전형의 반도체 기판과, 상기 반도체기판의 주표면상에 평행으로 뻗은 복수의 워드선과 상기 워드선에 직교하는 방향으로 뻗은 복수의 비트선과 상기 워드선 및 상기 비트선과에 경사로 교차하는 방향으로 배치된 복수의 메모리셀과를 구비하고 상기 메모리셀의 각각은 상기 워드선에 대하여 경사로 교차하는 방향으로 상기 반도체기판중에 형성된 한쌍의 제2도전형불순물영역과 상기 워드선의 일부로부터 이루어지는 게이트 전극층과를 포함하는 스위칭소자와, 인접하는 상기 비트선의 사이에 배치되고 그 일부가 상기 비트선보다 위쪽위치에 형성된 커패시터와를 포함하고 다시금 상기 커패시터는 상기 스위칭소자의 한쌍의 상기 제2도전형 불순물 영역의 한쪽에 접속되는 제1전극층과 상기 제1전극층의 표면상을 덮는 유전체층과 상기 유전체층의 표면을 덮는 제2전극층과를 구비하고 상기 비트선의 상부영역의 적어도 일부분에는 상기 커패시터의 제1 및 제2전극층의 어떠한 것도 존재하지 않는 절연층영역이 형성되어 있는 반도체 기억장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900017847A 1989-12-01 1990-11-05 반도체 기억장치 KR950010393B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1313744A JP2528719B2 (ja) 1989-12-01 1989-12-01 半導体記憶装置
JP1-313744 1989-12-01

Publications (2)

Publication Number Publication Date
KR910013555A true KR910013555A (ko) 1991-08-08
KR950010393B1 KR950010393B1 (ko) 1995-09-16

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900017847A KR950010393B1 (ko) 1989-12-01 1990-11-05 반도체 기억장치

Country Status (4)

Country Link
US (1) US5045899A (ko)
JP (1) JP2528719B2 (ko)
KR (1) KR950010393B1 (ko)
DE (1) DE4018809A1 (ko)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5180683A (en) * 1988-06-10 1993-01-19 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing stacked capacitor type semiconductor memory device
US5200635A (en) * 1988-12-21 1993-04-06 Hitachi, Ltd. Semiconductor device having a low-resistivity planar wiring structure
JP2792211B2 (ja) * 1990-07-06 1998-09-03 日本電気株式会社 半導体記憶装置
DE4131078A1 (de) * 1990-11-19 1992-05-21 Micron Technology Inc Kondensatorstrukturen fuer dram-zellen
US6002149A (en) * 1990-11-19 1999-12-14 Micron Technology, Inc. Capacitor structures for memory cells
CA2056010C (en) * 1990-11-27 1997-05-27 Minoru Maehara Inverter device for stable, high power-factor input current supply
KR950011636B1 (ko) * 1992-03-04 1995-10-07 금성일렉트론주식회사 개선된 레이아웃을 갖는 다이내믹 랜덤 액세스 메모리와 그것의 메모리셀 배치방법
US5162248A (en) * 1992-03-13 1992-11-10 Micron Technology, Inc. Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
US5270241A (en) * 1992-03-13 1993-12-14 Micron Technology, Inc. Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
USRE39665E1 (en) 1992-03-13 2007-05-29 Micron Technology, Inc. Optimized container stacked capacitor DRAM cell utilizing sacrificial oxide deposition and chemical mechanical polishing
US5352622A (en) * 1992-04-08 1994-10-04 National Semiconductor Corporation Stacked capacitor with a thin film ceramic oxide layer
JP2769664B2 (ja) * 1992-05-25 1998-06-25 三菱電機株式会社 半導体記憶装置およびその製造方法
US5313089A (en) * 1992-05-26 1994-05-17 Motorola, Inc. Capacitor and a memory cell formed therefrom
US5198386A (en) * 1992-06-08 1993-03-30 Micron Technology, Inc. Method of making stacked capacitors for DRAM cell
US5539612A (en) * 1992-09-08 1996-07-23 Texas Instruments Incorporated Intermediate structure for forming a storage capacitor
JPH06243677A (ja) * 1993-02-19 1994-09-02 Hitachi Ltd 半導体記憶装置とメモリ装置及びその品種設定方法
JP2570100B2 (ja) * 1993-05-16 1997-01-08 日本電気株式会社 半導体記憶装置
JP3090833B2 (ja) * 1993-12-28 2000-09-25 株式会社東芝 半導体記憶装置
KR0136994B1 (ko) * 1994-10-27 1998-04-24 김주용 반도체 소자의 캐패시터 구조 및 그 제조방법
KR100190834B1 (ko) * 1994-12-08 1999-06-01 다니구찌 이찌로오, 기타오카 다카시 반도체장치및그제조방법
US5438011A (en) * 1995-03-03 1995-08-01 Micron Technology, Inc. Method of forming a capacitor using a photoresist contact sidewall having standing wave ripples
US5508223A (en) * 1995-05-05 1996-04-16 Vanguard International Semiconductor Corporation Method for manufacturing DRAM cell with fork-shaped capacitor
US5702970A (en) * 1995-06-26 1997-12-30 Hyundai Electronics Industries Co., Ltd. Method for fabricating a capacitor of a semiconductor device
US5825061A (en) * 1995-12-06 1998-10-20 Utron Technology Inc. Channel-type stack capacitor for DRAM cell
US6083831A (en) * 1996-03-26 2000-07-04 Micron Technology, Inc. Semiconductor processing method of forming a contact pedestal, of forming a storage node of a capacitor
US6297129B2 (en) * 1997-04-22 2001-10-02 Micron Technology, Inc. Methods of forming integrated circuitry, and methods of forming dynamic random access memory circuitry
US6008084A (en) * 1998-02-27 1999-12-28 Vanguard International Semiconductor Corporation Method for fabricating low resistance bit line structures, along with bit line structures exhibiting low bit line to bit line coupling capacitance
US6174767B1 (en) 1998-05-11 2001-01-16 Vanguard International Semiconductor Corporation Method of fabrication of capacitor and bit-line at same level for 8F2 DRAM cell with minimum bit-line coupling noise
US6323081B1 (en) 1998-09-03 2001-11-27 Micron Technology, Inc. Diffusion barrier layers and methods of forming same
US6204172B1 (en) * 1998-09-03 2001-03-20 Micron Technology, Inc. Low temperature deposition of barrier layers
US5895239A (en) * 1998-09-14 1999-04-20 Vanguard International Semiconductor Corporation Method for fabricating dynamic random access memory (DRAM) by simultaneous formation of tungsten bit lines and tungsten landing plug contacts
US5893734A (en) * 1998-09-14 1999-04-13 Vanguard International Semiconductor Corporation Method for fabricating capacitor-under-bit line (CUB) dynamic random access memory (DRAM) using tungsten landing plug contacts
US6911687B1 (en) * 2000-06-21 2005-06-28 Infineon Technologies Ag Buried bit line-field isolation defined active semiconductor areas
US6272054B1 (en) 2000-10-31 2001-08-07 International Business Machines Corporation Twin-cell memory architecture with shielded bitlines for embedded memory applications
US6710391B2 (en) * 2002-06-26 2004-03-23 Texas Instruments Incorporated Integrated DRAM process/structure using contact pillars
US7319602B1 (en) 2004-07-01 2008-01-15 Netlogic Microsystems, Inc Content addressable memory with twisted data lines
US7944724B2 (en) * 2009-04-28 2011-05-17 Netlogic Microsystems, Inc. Ternary content addressable memory having reduced leakage effects
US7920397B1 (en) 2010-04-30 2011-04-05 Netlogic Microsystems, Inc. Memory device having bit line leakage compensation
US8878270B2 (en) * 2011-04-15 2014-11-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor memory device

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3177173D1 (de) * 1980-01-25 1990-05-23 Toshiba Kawasaki Kk Halbleiterspeichervorrichtung.
JPS57208691A (en) * 1981-06-15 1982-12-21 Mitsubishi Electric Corp Semiconductor memory
JPH0618257B2 (ja) * 1984-04-28 1994-03-09 富士通株式会社 半導体記憶装置の製造方法
JPS61251064A (ja) * 1985-04-30 1986-11-08 Toshiba Corp 半導体集積回路
JPS61258467A (ja) * 1985-05-13 1986-11-15 Hitachi Ltd 半導体記憶装置
JPS62136069A (ja) * 1985-12-10 1987-06-19 Hitachi Ltd 半導体装置およびその製造方法
JP2702121B2 (ja) * 1987-02-25 1998-01-21 日本電気株式会社 半導体記憶装置
JP2741857B2 (ja) * 1987-05-11 1998-04-22 株式会社日立製作所 半導体記憶装置
KR910009805B1 (ko) * 1987-11-25 1991-11-30 후지쓰 가부시끼가이샤 다이나믹 랜덤 액세스 메모리 장치와 그의 제조방법
JP2590171B2 (ja) * 1988-01-08 1997-03-12 株式会社日立製作所 半導体記憶装置
JP2755591B2 (ja) * 1988-03-25 1998-05-20 株式会社東芝 半導体記憶装置
JP2645069B2 (ja) * 1988-04-07 1997-08-25 富士通株式会社 半導体集積回路装置
JPH01302851A (ja) * 1988-05-31 1989-12-06 Fujitsu Ltd 半導体メモリのメモリセル構造
DE3918924C2 (de) * 1988-06-10 1996-03-21 Mitsubishi Electric Corp Herstellungsverfahren für eine Halbleiterspeichereinrichtung
JP2731197B2 (ja) * 1988-11-28 1998-03-25 株式会社東芝 半導体記憶装置およびその製造方法

Also Published As

Publication number Publication date
DE4018809C2 (ko) 1993-07-29
DE4018809A1 (de) 1991-06-06
US5045899A (en) 1991-09-03
JP2528719B2 (ja) 1996-08-28
JPH03173470A (ja) 1991-07-26
KR950010393B1 (ko) 1995-09-16

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