KR910001945A - 반도체장치 - Google Patents
반도체장치 Download PDFInfo
- Publication number
- KR910001945A KR910001945A KR1019900009459A KR900009459A KR910001945A KR 910001945 A KR910001945 A KR 910001945A KR 1019900009459 A KR1019900009459 A KR 1019900009459A KR 900009459 A KR900009459 A KR 900009459A KR 910001945 A KR910001945 A KR 910001945A
- Authority
- KR
- South Korea
- Prior art keywords
- standard
- cell
- wiring
- semiconductor device
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1의 실시예에 관계되는 반도체장치의 평면도.
제2도 내지 제7도는 본 발명의 변형예에 관계되는 각각의 스탠다드셀의 평면도.
Claims (4)
- 스탠다드셀 방식에서의 자동배치 배선에 의해서 스탠다드셀간 배선(9, 10)의 접속을 행한 반도체장치에 있어서, 스탠다드 셀(1)면상에서 상기 스탠다드셀간 배선끼리 접속되어 있는 것을 특징으로 하는 반도체장치.
- 제1항에 있어서, 상기 스탠다드 셀간 배선(9, 10)이 스탠다드 셀내 배선(3, 4)과 다른 도전층으로 이루어진 것을 특징으로 하는 반도체장치.
- 제2항에 있어서, 상기 스탠다드 셀간 배선을 구성하는 도전층이 제3층(9)과, 제4층(10)의 도전층으로 이루어지고, 상기 스탠다드 셀내 배선을 구성하는 도전층이 제1층(2)과 제2층(3)으로 이루어진 것을 특징으로 하는 반도체장치.
- 제1항에 있어서, 상기 스탠다드 셀에서, 이 스탠다드 셀내의 능동소자에 대해서 개공되어 있는 바이어홀(5)이 소정의 폭을 가지는 직선상에 설치된 바이어홀 개공영역(4)내에 각각 개공되어 있는 것을 특징으로 하는 반도체장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1-163197 | 1989-06-26 | ||
JP1163197A JPH0329342A (ja) | 1989-06-26 | 1989-06-26 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR910001945A true KR910001945A (ko) | 1991-01-31 |
Family
ID=15769122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900009459A KR910001945A (ko) | 1989-06-26 | 1990-06-26 | 반도체장치 |
Country Status (4)
Country | Link |
---|---|
US (1) | US5111271A (ko) |
EP (1) | EP0405460A3 (ko) |
JP (1) | JPH0329342A (ko) |
KR (1) | KR910001945A (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100437344B1 (ko) * | 2001-08-20 | 2004-06-25 | 한국에너지기술연구원 | 먼지가 내부로 침투하는 것을 방지하는 표면층을 구비한 집진필터와 그 제조방법 및 장치 |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3027990B2 (ja) * | 1991-03-18 | 2000-04-04 | 富士通株式会社 | 半導体装置の製造方法 |
US5576554A (en) * | 1991-11-05 | 1996-11-19 | Monolithic System Technology, Inc. | Wafer-scale integrated circuit interconnect structure architecture |
US5498990A (en) * | 1991-11-05 | 1996-03-12 | Monolithic System Technology, Inc. | Reduced CMOS-swing clamping circuit for bus lines |
US5831467A (en) * | 1991-11-05 | 1998-11-03 | Monolithic System Technology, Inc. | Termination circuit with power-down mode for use in circuit module architecture |
DE69226150T2 (de) * | 1991-11-05 | 1999-02-18 | Hsu Fu Chieh | Redundanzarchitektur für Schaltungsmodul |
JPH08500687A (ja) * | 1992-08-10 | 1996-01-23 | モノリシック・システム・テクノロジー・インコーポレイテッド | ウェハ規模の集積化のためのフォルトトレラントな高速度のバス装置及びバスインタフェース |
US5536955A (en) * | 1993-03-29 | 1996-07-16 | Toppan Electronics (Usa) Inc. | Electronic devices for use in generating integrated circuit structures and method therefor |
US5440153A (en) * | 1994-04-01 | 1995-08-08 | United Technologies Corporation | Array architecture with enhanced routing for linear asics |
JP3185540B2 (ja) * | 1994-06-10 | 2001-07-11 | 松下電器産業株式会社 | 半導体集積回路 |
US5655113A (en) | 1994-07-05 | 1997-08-05 | Monolithic System Technology, Inc. | Resynchronization circuit for a memory system and method of operating same |
US5742099A (en) * | 1994-09-29 | 1998-04-21 | Intel Corporation | Power bus for an integrated circuit including end-to-end arranged segments providing power and ground |
US5789807A (en) * | 1996-10-15 | 1998-08-04 | International Business Machines Corporation | On-chip power distribution for improved decoupling |
US5894142A (en) * | 1996-12-11 | 1999-04-13 | Hewlett-Packard Company | Routing for integrated circuits |
US6025616A (en) * | 1997-06-25 | 2000-02-15 | Honeywell Inc. | Power distribution system for semiconductor die |
JP3349989B2 (ja) * | 1999-06-18 | 2002-11-25 | エヌイーシーマイクロシステム株式会社 | 半導体集積回路装置及びそのレイアウト方法及び装置 |
US6892370B2 (en) * | 2003-04-02 | 2005-05-10 | Silicon Design Systems Ltd. | Computerized standard cell library for designing integrated circuits (ICs) with high metal layer intra cell signal wiring, and ICs including same |
US8816403B2 (en) * | 2011-09-21 | 2014-08-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Efficient semiconductor device cell layout utilizing underlying local connective features |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51147982A (en) * | 1975-06-13 | 1976-12-18 | Nec Corp | Integrated circuit |
JPS5319775A (en) * | 1976-08-09 | 1978-02-23 | Hitachi Ltd | Large scale integrated circuit |
US4969029A (en) * | 1977-11-01 | 1990-11-06 | Fujitsu Limited | Cellular integrated circuit and hierarchial method |
JPS5878450A (ja) * | 1981-11-04 | 1983-05-12 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路装置 |
JPS5887854A (ja) * | 1981-11-20 | 1983-05-25 | Nec Corp | マスタスライス方式lsi基板 |
JPS5911670A (ja) * | 1982-07-12 | 1984-01-21 | Toshiba Corp | 半導体集積回路装置 |
JPS607147A (ja) * | 1983-06-24 | 1985-01-14 | Mitsubishi Electric Corp | 半導体装置 |
JPS61292341A (ja) * | 1985-06-20 | 1986-12-23 | Toshiba Corp | 半導体集積回路 |
JPS628538A (ja) * | 1985-07-05 | 1987-01-16 | Hitachi Ltd | 半導体集積回路装置 |
JPS6278848A (ja) * | 1985-09-30 | 1987-04-11 | Nec Corp | 大規模半導体集積回路 |
JPS62177940A (ja) * | 1986-01-31 | 1987-08-04 | Toshiba Corp | 半導体論理集積回路装置 |
JPS62273751A (ja) * | 1986-05-21 | 1987-11-27 | Nec Corp | 集積回路 |
US4910574A (en) * | 1987-04-30 | 1990-03-20 | Ibm Corporation | Porous circuit macro for semiconductor integrated circuits |
JPH0812882B2 (ja) * | 1987-08-25 | 1996-02-07 | 富士通株式会社 | 半導体集積回路 |
-
1989
- 1989-06-26 JP JP1163197A patent/JPH0329342A/ja active Pending
-
1990
- 1990-06-25 US US07/543,128 patent/US5111271A/en not_active Expired - Lifetime
- 1990-06-26 EP EP19900112150 patent/EP0405460A3/en not_active Withdrawn
- 1990-06-26 KR KR1019900009459A patent/KR910001945A/ko not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100437344B1 (ko) * | 2001-08-20 | 2004-06-25 | 한국에너지기술연구원 | 먼지가 내부로 침투하는 것을 방지하는 표면층을 구비한 집진필터와 그 제조방법 및 장치 |
Also Published As
Publication number | Publication date |
---|---|
EP0405460A2 (en) | 1991-01-02 |
EP0405460A3 (en) | 1991-12-27 |
US5111271A (en) | 1992-05-05 |
JPH0329342A (ja) | 1991-02-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
SUBM | Surrender of laid-open application requested |