EP0351819A3 - Standard cells with flip-flops - Google Patents

Standard cells with flip-flops Download PDF

Info

Publication number
EP0351819A3
EP0351819A3 EP19890113243 EP89113243A EP0351819A3 EP 0351819 A3 EP0351819 A3 EP 0351819A3 EP 19890113243 EP19890113243 EP 19890113243 EP 89113243 A EP89113243 A EP 89113243A EP 0351819 A3 EP0351819 A3 EP 0351819A3
Authority
EP
European Patent Office
Prior art keywords
flops
flip
standard cells
cells
standard
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP19890113243
Other versions
EP0351819B1 (en
EP0351819A2 (en
Inventor
Tohru Sasaki
Takeji Tokumaru
Tsuneaki Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of EP0351819A2 publication Critical patent/EP0351819A2/en
Publication of EP0351819A3 publication Critical patent/EP0351819A3/en
Application granted granted Critical
Publication of EP0351819B1 publication Critical patent/EP0351819B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
EP89113243A 1988-07-19 1989-07-19 Standard cells with flip-flops Expired - Lifetime EP0351819B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP178214/88 1988-07-19
JP63178214A JPH0229124A (en) 1988-07-19 1988-07-19 Standard cell

Publications (3)

Publication Number Publication Date
EP0351819A2 EP0351819A2 (en) 1990-01-24
EP0351819A3 true EP0351819A3 (en) 1990-11-28
EP0351819B1 EP0351819B1 (en) 1995-09-13

Family

ID=16044580

Family Applications (1)

Application Number Title Priority Date Filing Date
EP89113243A Expired - Lifetime EP0351819B1 (en) 1988-07-19 1989-07-19 Standard cells with flip-flops

Country Status (5)

Country Link
US (1) US5029279A (en)
EP (1) EP0351819B1 (en)
JP (1) JPH0229124A (en)
KR (1) KR920010213B1 (en)
DE (1) DE68924213T2 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2622612B2 (en) * 1989-11-14 1997-06-18 三菱電機株式会社 Integrated circuit
JPH03257949A (en) * 1990-03-06 1991-11-18 Advanced Micro Devices Inc Delay circuit
US5208764A (en) * 1990-10-29 1993-05-04 Sun Microsystems, Inc. Method for optimizing automatic place and route layout for full scan circuits
TW198159B (en) * 1991-05-31 1993-01-11 Philips Gloeicampenfabrieken Nv
JP3026387B2 (en) * 1991-08-23 2000-03-27 沖電気工業株式会社 Semiconductor integrated circuit
US5396129A (en) * 1992-05-25 1995-03-07 Matsushita Electronics Corporation Semiconductor integrated circuit apparatus comprising clock signal line formed in a ring shape
US5508938A (en) * 1992-08-13 1996-04-16 Fujitsu Limited Special interconnect layer employing offset trace layout for advanced multi-chip module packages
US5387825A (en) * 1992-08-20 1995-02-07 Texas Instruments Incorporated Glitch-eliminator circuit
JP3048471B2 (en) * 1992-09-08 2000-06-05 沖電気工業株式会社 Clock supply circuit and clock skew adjustment method
EP0613074B1 (en) * 1992-12-28 1998-04-01 Advanced Micro Devices, Inc. Microprocessor circuit having two timing signals
US5444407A (en) * 1992-12-28 1995-08-22 Advanced Micro Devices, Inc. Microprocessor with distributed clock generators
US5444406A (en) * 1993-02-08 1995-08-22 Advanced Micro Devices, Inc. Self-adjusting variable drive strength buffer circuit and method for controlling the drive strength of a buffer circuit
DE4422784C2 (en) * 1994-06-29 1999-05-27 Texas Instruments Deutschland Circuit arrangement with at least one circuit unit such as a register, a memory cell, a memory arrangement or the like
US5742832A (en) * 1996-02-09 1998-04-21 Advanced Micro Devices Computer system with programmable driver output's strengths responsive to control signal matching preassigned address range
US6211703B1 (en) * 1996-06-07 2001-04-03 Hitachi, Ltd. Signal transmission system
JPH11186506A (en) * 1997-12-24 1999-07-09 Mitsubishi Electric Corp Integrated circuit
JP2007299800A (en) 2006-04-27 2007-11-15 Nec Electronics Corp Semiconductor integrated circuit device
US8018052B2 (en) * 2007-06-29 2011-09-13 Stats Chippac Ltd. Integrated circuit package system with side substrate having a top layer
JP2009152822A (en) * 2007-12-20 2009-07-09 Spansion Llc Storage device
US11095272B2 (en) 2018-09-21 2021-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Flip-flop cell

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2229123A1 (en) * 1971-06-30 1973-01-11 Ibm DYNAMICALLY OPERATED FIELD EFFECT TRANSISTOR ARRANGEMENT
EP0006958A1 (en) * 1977-12-30 1980-01-23 Fujitsu Limited Complementary mis-semiconductor integrated circuits

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55115352A (en) * 1979-02-27 1980-09-05 Fujitsu Ltd Clock distributing circuit of ic device
JPS5969948A (en) * 1982-10-15 1984-04-20 Fujitsu Ltd Master slice type semiconductor integrated circuit
US4694403A (en) * 1983-08-25 1987-09-15 Nec Corporation Equalized capacitance wiring method for LSI circuits
JPS6341048A (en) * 1986-08-06 1988-02-22 Mitsubishi Electric Corp Standard cell system large-scale integrated circuit
JPH0815210B2 (en) * 1987-06-04 1996-02-14 日本電気株式会社 Master slice type integrated circuit
JPH0828421B2 (en) * 1987-08-27 1996-03-21 株式会社東芝 Semiconductor integrated circuit device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2229123A1 (en) * 1971-06-30 1973-01-11 Ibm DYNAMICALLY OPERATED FIELD EFFECT TRANSISTOR ARRANGEMENT
EP0006958A1 (en) * 1977-12-30 1980-01-23 Fujitsu Limited Complementary mis-semiconductor integrated circuits

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
I.E.E.E. JOURNAL OF SOLID-STATE CIRCUITS, vol. SC-22, no. 2, April 1987, pages 190-197, IEEE, New York, NY, US; A.M. MARTINEZ et al.: "Compilation of standard-cell libraries" *
PATENT ABSTRACTS OF JAPAN, vol. 4, no. 165 (E-34)[647], 15th November 1980; & JP-A-55 115 352 (FUJITSU K.K.) 05-09-1980 *

Also Published As

Publication number Publication date
EP0351819B1 (en) 1995-09-13
EP0351819A2 (en) 1990-01-24
DE68924213T2 (en) 1996-04-04
JPH0481895B2 (en) 1992-12-25
KR900002564A (en) 1990-02-28
KR920010213B1 (en) 1992-11-21
DE68924213D1 (en) 1995-10-19
US5029279A (en) 1991-07-02
JPH0229124A (en) 1990-01-31

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